PDF PPC405EZ Data sheet ( Hoja de datos )

Número de pieza	PPC405EZ
Descripción	PowerPC 405EZ Embedded Processor
Fabricantes	Applied Micro Circuits Corporation
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Part Number 405EZ Revision 1.27 - August 22, 2007 405EZ PowerPC 405EZ Embedded Processor Preliminary Data Sheet Features • AMCC PowerPC® 405 32-bit RISC processor core operating at up to 416MHz • On-chip 32-bit peripheral bus (OPB) operating at up to 83 MHz • On-chip 64-bit processor local bus (PLB) www.DataSohpeeert4aUti.ncgomat up to 166MHz • 8-bit direct interface for NAND Flash devices • 32KB of on-chip, high-speed SRAM accessible by CPU and DMA • Inter-chip connectivity (SPI and IIC) • External 8-,16-, or 32-bit peripheral bus (EBC) operating at up to 83MHz • Boot from IIC bootstrap controller, EBC, NAND Flash, and SPI • DMA support for all on-chip slaves and external bus, including on-chip SRAM, ADC, DAC, UARTs, and devices on the external peripheral bus • One 10/100 Mbps Ethernet MII interface (half- and full-duplex) to external PHY • Three USB 1.1 ports: two Host and one Device with Full-Speed on-chip PHYs • Programmable universal interrupt controller (UIC) • IEEE 1588 Precision Timing Protocol (PTP) controller • Chameleon Timer™ and pulse width modulator (PWM) • Analog-to-Digital Converter (ADC) with eight inputs and 10-bit resolution at 300k samples/sec • Digital-to-Analog Converter (DAC) with one input and 10-bit resolution at 30M samples/sec • Two CAN 2.0B protocol and ISO 11898-1 compliant channels • Two serial ports (16750 compatible UART) • One IIC interface operating at up to 400kHz and supporting all standard IIC EEPROMs • One SPI (SCP) synchronous full-duplex channel operating at up to 40 MHz • 54 general purpose I/Os (GPIOs), each with programmable interrupts and outputs • Supports JTAG for board-level testing • System power management, low power dissipation and small form factor • RoHS compliant (lead-free) Description With speeds up to 416MHz, a flexible on-chip and off- chip memory architecture, a combination of an ADC, a DAC, a programmable Chameleon Timer/PWM, an IEEE 1588 PTP, and a diverse communications package that includes USB 1.1, Ethernet, and CAN, the PowerPC 405EZ embedded processor provides a low power and small footprint system-on-a-chip solution for a wide range of high performance, cost- constrained embedded applications. This includes industrial control, high-precision AC/DC and servo drive control, instrumentation, data acquisition, industrial automation, building and enclosure management, commercial and retail systems, Internet appliances, and intelligent USB peripherals. It is an easily programmable general purpose, 32-bit RISC controller that offers an upgrade path for applications in need of performance and connectivity improvements. Technology: CU-11 CMOS, 130nm Package: 324-ball, 23mm×23mm, lead-free, plastic ball grid array (EPBGA), 1mm ball pitch Typical Power (Est.): 1.05W @ 166 MHz;1.48W @ 416 MHz AMCC Proprietary 1 1 page PPC405EZ – PowerPC 405EZ Embedded Processor Block Diagram Figure 1. PPC405EZ Embedded Controller Functional Block Diagram Revision 1.27 - August 22, 2007 Preliminary Data Sheet Universal Interrupt Controller Clock Control Reset Power Mgmt 32 KB SRAM www.DataSheet4U.com Timers MMU D-OCM I-OCM PowerPC 405 Core JTAG Trace 16KB D-Cache 16KB I-Cache DCRs DCR Bus OCM Ctrl Arbiter UART CAN x2 x2 IIC/ BSC SPI (SCP) GPIO Timer/ PWM DAC On-chip Peripheral Bus (OPB) ADC DMA Controller (4-Channel) OPB/PLB Bridges MAL Ethernet USB 1.1 10/100 Host/Dev IEEE 1588 PTP Arbiter Processor Local Bus (PLB) 64 bit, PLB3 External Bus Controller NAND Flash Controller PHY MII The PPC405EZ is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture. AMCC Proprietary 5 5 Page PPC405EZ – PowerPC 405EZ Embedded Processor Universal Serial Bus Specification Revision 1.27 - August 22, 2007 Preliminary Data Sheet Controller Area Network (CAN) The CAN controller module supports the concept of mailboxes. It contains 32 receive buffers, each one with its own message filter, and 32 transmit buffers with a prioritized arbitration scheme. For optimal support of Higher Level Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes. Features include: • CAN 2.0B protocol compliant • ISO 11898-1 compliant • 32 Transmit message holding registers, programmable priority arbitration • Message abort command supported www.Da•taS3h2eeRt4eUc.eciovme buffers (each with own message filter) – Message filtering: ID, IDE, Remote Transmission Request (RTR), data byte 1, and data byte 2 • Message buffers can be linked together to build bigger message arrays • Automatic RTR response handler • Message Abort command supported • Maximum baud rate of 1Mbps with 8MHz system clock • Listen-only for debugging supported • Global masking supported • 32-bit OPB slave interface • Internal loopback UART The Universal Asynchronous Receiver/Transmitter (UART) interface provides two ports. The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial conversion on data received from the processor. Features include: • Two ports (UART_0 and UART_1) • Software modem control functions (CTS, RTS, DSR, DTR, RI, DCD) on UART_0 • Programmable auto flow (data flow controlled by RTS and CTS signals) • 5-, 6-, 7-, or 8-bit characters • Programmable start, stop, parity bit insertion • 64 byte FIFOs to buffer Tx and Rx data • LIN sub-bus specification compliant - line break generation/detection and false start bit detection • Programmable internal/external loopback capabilities • Low Power and Sleep mode • Register conformance (after reset) to configuration of the NS16450 register set • Hold and shift registers (eliminate need for precise synchronization between processor and serial data in character mode) • Complete status reporting • Full prioritized interrupt system controls • Independently controlled transmit, receive, line status, and data set interrupts • Programmable baud generator (divides serial clock input and generates 16x clock) • Ability to add/delete standard asynchronous communication bits such as start, stop, and parity to/from serial data • Even, odd, or no-parity bit generation and detection • 1-, 1.5-, or 2-stop bit generation • Variable baud rate • Internal diagnostic capability AMCC Proprietary 11 11 Page

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