PDF PPC405EP Data sheet ( Hoja de datos )

Número de pieza	PPC405EP
Descripción	Power PC 405EP Embedded Processor
Fabricantes	Applied Micro Circuits
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No Preview Available ! Part Number PPC405EP Revision 1.02 – January 10, 2005 PPC405EP PowerPC 405EP Embedded Processor Data Sheet Features • AMCC PowerPC® 405 32-bit RISC processor core operating up to 333MHz with 16KB D- and I-caches • PC-133 synchronous DRAM (SDRAM) inter- face - 32-bit interface for non-ECC applications • 4KB on-chip memory (OCM) • External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8- or 16-bit SRAM and external peripherals - Up to five devices • DMA support for memory and UARTs. - Scatter-gather chaining supported - Four channels • PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Asynchronous PCI Bus interface - Internal or external PCI Bus Arbiter • Two Ethernet 10/100Mbps (full-duplex) ports with media independent interface (MII) • Programmable interrupt controller supports seven external and 19 internal edge-triggered or level-sensitive interrupts • Programmable timers • Software accessible event counters • Two serial ports (16750 compatible UART) • One IIC interface • General purpose I/O (GPIO) available • Supports JTAG for board level testing • Internal processor local Bus (PLB) runs at SDRAM interface frequency • Supports PowerPC processor boot from PCI memory Description Designed specifically to address embedded applications, the PowerPC 405EP (PPC405EP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: CMOS SA-27E, 0.18 µm (0.11 µm Leff) Package: 31mm, 385-ball, enhanced plastic ball grid array (E-PBGA) Power (typical): 0.72W at 266MHz AMCC 1 1 page PPC405EP – PowerPC 405EP Embedded Processor Revision 1.02 – January 10, 2005 Data Sheet Figure 1. PPC405EP Embedded Controller Functional Block Diagram Universal Interrupt Controller 16KB D-Cache Clock Control Reset Power Mgmt Timers MMU DOCM IOCM PPC405 Processor Core JTAG DCU Trace ICU OCM SRAM OCM Control DCR Bus Event Counters DCRs GPIO IIC GPT UART x2 16KB Arb I-Cache On-chip Peripheral Bus (OPB) CoDnMtroAller (4-Channel) OPB Bridge MAL Ethernet x2 Arb Processor Local Bus (PLB) SDRAM Controller 13-bit addr 32-bit data External Bus Controller 29-bit addr 16-bit data PCI Bridge 66 MHz max (async) MII The PPC405EP is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture. AMCC 5 5 Page PPC405EP – PowerPC 405EP Embedded Processor Revision 1.02 – January 10, 2005 Data Sheet 10/100 Mbps Ethernet MAC • Two ports capable of handling full/half duplex 100Mbps and 10Mbps operation • Uses the medium independent interface (MII) to the physical layer (PHY not included on chip) JTAG • IEEE 1149.1 test access port • IBM RISCWatch debugger support • JTAG Boundary Scan Description Language (BSDL) AMCC 11 11 Page

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