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PDF LTC1852 Data sheet ( Hoja de datos )
| Número de pieza | LTC1852 | |
| Descripción | Sampling ADCs | |
| Fabricantes | Linear Technology | |
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LTC1852/LTC1853
8-Channel, 10-Bit/12-Bit,
400ksps, Low Power, Sampling ADCs
FEATURES
n Flexible 8-Channel Multiplexer
Single-Ended or Differential Inputs
Two Gain Ranges
Unipolar or Bipolar Operation
n Scan Mode and Programmable Sequencer
Eliminate Configuration Software Overhead
wwwn.DaLtoawShPeeotw4Ue.rc:o3mmW at 250ksps
n 2.7V to 5.5V Supply Range
n Internal or External Reference Operation
n Parallel Output Includes MUX Address
n Nap and Sleep Shutdown Modes
n Pin Compatible up-grade 1.25Msps 10-Bit LTC1850
and 12-Bit LTC1851
APPLICATIONS
n High Speed Data Acquisition
n Test and Measurement
n Imaging Systems
n Telecommunications
n Industrial Process Control
n Spectrum Analysis
DESCRIPTION
The 10-bit LTC®1852 and 12-bit LTC1853 are complete
8-channel data acquisition systems. They include a flexible
8-channel multiplexer, a 400ksps successive approxima-
tion analog-to-digital converter, an internal reference and a
parallel output interface. The multiplexer can be configured
for single-ended or differential inputs, two gain ranges and
unipolar or bipolar operation. The ADCs have a scan mode
that will repeatedly cycle through all 8 multiplexer channels
and can also be programmed to sequence through up to
16 addresses and configurations. The sequence can also
be read back from internal memory.
The reference and buffer amplifier provide pin strappable
ranges of 4.096V, 2.5V and 2.048V. The parallel output
includes the 10-bit or 12-bit conversion result plus the
4-bit multiplexer address. The digital outputs are pow-
ered from a separate supply allowing for easy interface
to 3V digital logic. Typical power consumption is 10mW
at 400ksps from a single 5V supply and 3mW at 250ksps
from a single 3V supply.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRAM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
REFOUT
8-CHANNEL
MULTIPLEXER
2.5V
REFERENCE
LTC1853
INTERNAL
CLOCK
+ 12-BIT
–
SAMPLING
ADC
REFIN
REF AMP
REFCOMP
CONTROL LOGIC
AND
PROGRAMMABLE
SEQUENCER
DATA
LATCHES
OUTPUT
DRIVERS
M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OVDD
BUSY
DIFFOUT/S6
A2OUT/S5
A1OUT/S4
A0OUT/S3
D11/S2
D10/S1
D9/S0
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
18523 BD
Integral Linearity
1.0
0.5
0
–0.5
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
1852 F01
18523fa
1
1 page  
LTC1852/LTC1853
POWER REQUIREMENTS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
VDD Analog Positive Supply Voltage
(Note 10)
● 2.7
5.5 V
OVDD
Output Positive Supply Voltage
(Note 10)
● 2.7
5.5 V
IDD
PDISS
IDDPD
Positive Supply Current
Power Dissipation
Power Down Positive Supply Current
Nap Mode
Sleep Mode
VDD = OVDD = 5V, fS = 400kHz
VDD = OVDD = 2.7V, fS = 250kHz
VDD = OVDD = 5V, fS = 400kHz
VDD = OVDD = 2.7V, fS = 250kHz
SHDN = Low, CS = Low
SHDN = Low, CS = High
●
●
●
●
23
0.83 1.33
mA
mA
10 15 mW
2.25 4 mW
0.5 mA
20 μA
www.DataSheePt4oUw.ecroDmown Power Dissipation
VDD = VDD = OVDD = 5V, fS = 400kHz
Nap Mode
SHDN = Low, CS = Low
2.5 mW
Sleep Mode
SHDN = Low, CS = High
0.1 mW
Power Down Power Dissipation
VDD = VDD = OVDD = 3V, fS = 250kHz
Nap Mode
SHDN = Low, CS = Low
1.5 mW
Sleep Mode
SHDN = Low, CS = High
0.06 mW
TIMING CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
fSAMPLE(MAX) Maximum Sampling Frequency
Acquisition + Conversion
tCONV
tACQ
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Conversion Time
Acquisition Time
CS to RD Setup Time
CS to CONVST Setup Time
CS to SHDN Setup Time
SHDN to CONVST Wake-Up Time
CONVST Low Time
CONVST to BUSY Delay
Data Ready Before BUSY
Delay Between Conversions
Wait Time RD After BUSY
Data Access Time After RD
t11 BUS Relinquish Time
t12 RD Low Time
CONDITIONS
VDD = 5.5V
VDD = 2.7V
VDD = 5.5V
VDD = 2.7V
VDD = 5.5V
VDD = 2.7V
(Note 13)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
Nap Mode (Note 10)
Sleep Mode (Note 10)
(Notes 10, 11)
CL = 25pF
(Note 10)
CL = 25pF
CL = 100pF
0°C to 70°C
– 40°C to 85°C
MIN
● 400
● 250
●
●
●
●
●
●0
● 10
● 50
●
20
● 15
● 50
● –5
●
●
●
●
● t10
TYP
200
200
10
10
35
20
25
10
MAX UNITS
kHz
kHz
2.5 μs
4.0 μs
2.0 μs
3.5 μs
150 ns
ns
ns
ns
ns
ms
ns
ns
60 ns
ns
ns
ns
ns
35 ns
45 ns
45 ns
60 ns
30 ns
35 ns
40 ns
ns
18523fa
5
5 Page 
LTC1852/LTC1853
APPLICATIONS INFORMATION
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa ± fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
( ) ( )www.DaIMtaDShefeat±4Uf.bco=m20Log
Amplitude at
Amplitude
fa ±
at fa
fb
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral
component excluding the input signal and DC. This value
is expressed in decibels relative to the RMS value of a
full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB for the LTC1853 (11
effective bits) or 56dB for the LTC1852 (9 effective bits).
The LTC1852/LTC1853 have been designed to optimize
input bandwidth, allowing the ADC to undersample input
signals with frequencies above the converter’s Nyquist fre-
quency. The noise floor stays very low at high frequencies;
S/(N + D) becomes dominated by distortion at frequencies
far beyond Nyquist.
ANALOG INPUT MULTIPLEXER
The analog input multiplexer is controlled using the
single-ended/differential pin (DIFF), three MUX address
pins (A2, A1, A0), the unipolar/bipolar pin (UNI/BIP) and
the gain select pin (PGA). The single-ended/differential
pin (DIFF) allows the user to configure the MUX as eight
single-ended channels relative to the analog input com-
mon pin (COM) when DIFF is low or as four differential
pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6
and CH7) when DIFF is high. The channels (and polarity in
the differential case) are selected using the MUX address
inputs as shown in Table 1. Unused inputs (including
the COM in the differential case) should be grounded to
prevent noise coupling.
Table 1. Multiplexer Address Table
MUX ADDRESS
SINGLE-ENDED CHANNEL SELECTION
DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0000 +
–
00 0 1
+
–
00 1 0
+
–
00 1 1
+
–
01 0 0
+–
01 0 1
+–
01 1 0
+–
01 1 1
+–
MUX ADDRESS
DIFFERENTIAL CHANNEL SELECTION
DIFF A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
1000 + –
*
1001 – +
*
10 1 0
+–
*
10 1 1
–+
*
11 0 0
+–
*
11 0 1
–+
*
11 1 0
+–*
11 1 1
–+*
*Not used in differential mode. Connect to AGND.
In addition to selecting the MUX channel, the LTC1852/
LTC1853 also allows the user to select between two gains
and unipolar or bipolar inputs for a total of four input spans.
PGA high selects a gain of 1 (the input span is equal to the
voltage on REFCOMP). PGA low selects a gain of 2 where
the input span is equal to half of the voltage on REFCOMP.
UNI/BIP low selects a unipolar input span, UNI/BIP high
selects a bipolar input span. Table 2 summarizes the pos-
sible input spans.
Table 2. Input Span Table
UNI/BIP PGA
INPUT SPAN
REFCOMP = 4.096V
0 0 0 – REFCOMP/2
0 – 2.048V
0 1 0 – REFCOMP
0 – 4.096V
1 0 ± REFCOMP/4
±1.024V
1 1 ±REFCOMP/2
±2.048V
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11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC1852.PDF ] | |
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