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PDF LTC1850 Data sheet ( Hoja de datos )
| Número de pieza | LTC1850 | |
| Descripción | 1.25Msps Sampling ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Flexible 8-Channel Multiplexer
s Single-Ended or Differential Inputs
s Two Gain Ranges Plus Unipolar and Bipolar
Operation
s 1.25Msps Sampling Rate
s Single 5V Supply and 40mW Power Dissipation
s Scan Mode and Programmable Sequencer
wwws.DaPtianSCheoemt4pUa.ctiobmle 10-Bit LTC1850 and 12-Bit LTC1851
s True Differential Inputs Reject Common Mode Noise
s Internal 2.5V Reference
s Parallel Output Includes MUX Address
s Easy Interface to 3V Logic
s Nap and Sleep Shutdown Modes
U
APPLICATIO S
s High Speed Data Acquisition
s Test and Measurement
s Imaging Systems
s Telecommunications
s Industrial Process Control
s Spectrum Analysis
LTC1850/LTC1851
8-Channel, 10-Bit/12-Bit,
1.25Msps Sampling ADCs
DESCRIPTIO
The 10-bit LTC®1850 and 12-bit LTC1851 are complete
8-channel data acquisition systems. They include a flex-
ible 8-channel multiplexer, a 1.25Msps successive approxi-
mation analog-to-digital converter with sample-and-hold,
an internal 2.5V reference and reference buffer amplifier,
and a parallel output interface. The multiplexer can be con-
figured for single-ended or differential inputs, two gain
ranges and unipolar or bipolar operation.
The ADCs have a scan mode that will repeatedly cycle
through all 8 multiplexer channels and can also be
programmed with a sequence of up to 16 addresses and
configurations that can be scanned in succession. The
sequence memory can also be read back. The reference
and buffer amplifier provide pin strappable ranges of
4.096V, 2.5V and 2.048V. The parallel output includes
the 10-bit or 12-bit conversion result plus the 4-bit
multiplexer address. The digital outputs are powered
from a separate supply allowing for easy interface to 3V
digital logic. Typical power consumption is 40mW at
1.25Msps from a single 5V supply.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
REFOUT
8-CHANNEL
MULTIPLEXER
2.5V
REFERENCE
REFIN
REFCOMP
REF AMP
LTC1851
INTERNAL
CLOCK
12-BIT
1.25Msps ADC
CONTROL LOGIC
AND
PROGRAMMABLE
SEQUENCER
DATA
LATCHES
OUTPUT
DRIVERS
M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OVDD
BUSY
DIFFOUT/S6
A2OUT/S5
A1OUT/S4
A0OUT/S3
D11/S2
D10/S1
D9/S0
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
1851 BD
Integral Linearity, LTC1851
1.00
0.50
0.00
–0.50
–1.00
0 512 1024 1536 2048 2560 3072 3584 4096
CODE
LTC1850/51 G01
18501f
1
1 page  
LTC1850/LTC1851
POWER REQUIRE E TS The q denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VDD
OVDD
IDD
PDISS
Positive Supply Voltage
Output Positive Supply Voltage
Positive Supply Current
Power Dissipation
Power Down Positive Supply Current
Nap Mode
Sleep Mode
(Note 10)
(Note 10)
VDD = VDD = OVDD = 5V,
fSAMPLE = 1.25MHz
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
q 4.75
5.25 V
q 2.7
5.25 V
q 8 10 mA
q 40 50 mW
1 mA
50 µA
Power Down Power Dissipation
www.DataSheet4NUap.cMomode
Sleep Mode
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
5 mW
0.25 mW
WU
TI I G CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency
Acquisition + Conversion
q 1.25
q
MHz
800 ns
tCONV
tACQ
t1
t2
t3
t4
Conversion Time
Acquisition Time
CS to RD Setup Time
CS to CONVST Setup Time
CS to SHDN Setup Time
SHDN to CONVST Wake-Up Time
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
Nap Mode (Note 10)
Sleep Mode, 10µF REFCOMP
Bypass Capacitor (Note 10)
q
q
q0
q 10
650
150
200
200
10
ns
ns
ns
ns
ns
ns
ms
t5 CONVST Low Time
t6 CONVST to BUSY Delay
(Notes 10, 11)
CL = 25pF
q 50
q
10
60
ns
ns
ns
t7 Data Ready Before BUSY
20
q 15
35
ns
ns
t8 Delay Between Conversions
t9 Wait Time RD After BUSY
t10 Data Access Time After RD
(Note 10)
CL = 25pF
q 50
q –5
20 35
q 45
ns
ns
ns
ns
CL = 100pF
25 45
ns
q 60 ns
t11 BUS Relinquish Time
0°C to 70°C
– 40°C to 85°C
10 30
ns
q 35 ns
q 40 ns
t12 RD Low Time
t13 CONVST High Time
t14 Latch Setup Time
t15 Latch Hold Time
t16 WR Low Time
(Note 10)
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
q t10
q 50
q 10
q 10
q 50
ns
ns
ns
ns
ns
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5 Page 
LTC1850/LTC1851
PI FU CTIO S
D9/S0 (Pin 23, LTC1851): Three-State Digital Data Out-
puts. Active when RD is low. Following a conversion, bit 9
of the present conversion is available on this pin. In
Readback mode, the end of sequence bit of the current
sequencer location (S0) is available on this pin. The output
swings between OVDD and OGND.
D6 to D0 (Pins 24 to 30, LTC1850): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OVDD and OGND.
wwwD.D8attoaSDhe0e(t4PUi.ncsom24 to 32, LTC1851): Three-State Digital
Data Outputs. Active when RD is low. The outputs swing
between OVDD and OGND.
NC (Pins 31, 32, LTC1850): No Connect. There is no
internal connection to these pins.
BUSY (Pin 33): Converter Busy Output. The BUSY output
has two functions. At the start of a conversion, BUSY will
go low and remain low until the conversion is completed.
The rising edge may be used to latch the output data. BUSY
will also go low while the part is in Program/Readback
mode (M1 high, M0 low) and remain low until M0 is
brought back high. The output swings between OVDD and
OGND.
OGND (Pin 34): Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OVDD (Pin 35): Digital Data Output Supply. Normally tied
to 5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10µF tantalum in parallel with 0.1µF ceramic
or 10µF ceramic. See Table 5.
M0 (Pin 36): Mode Select Pin 0. Used in conjunction with
M1 to select operating mode. See Table 5
PGA (Pin 37): Gain Select Input. A high logic level selects
gain = 1, a low logic level selects gain = 2.
UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low
selects a unipolar input span, a high logic level selects a
bipolar input span.
A0 to A2 (Pins 39 to 41): MUX Address Input Pins.
DIFF (Pin 42): Single-Ended/Differential Select Input. A
low logic level selects single-ended mode, a high logic
level selects differential mode.
WR (Pin 43): Write Input. In Direct Address mode, WR low
enables the MUX address and configuration input pins
(Pins 37 to 42). WR can be tied low or the rising edge of
WR can be used to latch the data. In Program mode, WR
is used to program the sequencer. WR low enables the
MUX address and configuration input pins (Pins 37 to 42).
The rising edge of WR latches the data and increments the
counter to the next sequencer location.
RD (Pin 44): Read Input. During normal operation, RD
enables the output drivers when CS is low. In Readback
mode (M1 high, M0 low), RD going low reads the current
sequencer location, RD high advances to the next sequencer
location.
CONVST (Pin 45): Conversion Start Input. This active low
signal starts a conversion on its falling edge.
CS (Pin 46): Chip Select Input. The chip select input must
be low for the ADC to recognize the CONVST and RD
inputs. If SHDN is low, a low logic level on CS selects Nap
mode; a high logic level on CS selects Sleep mode.
SHDN (Pin 47): Power Shutdown Input. A low logic level
will invoke the Shutdown mode selected by the CS pin. CS
low selects Nap mode, CS high selects Sleep mode. Tie
high if unused.
M1 (Pin 48): Mode Select Pin 1. Used in conjunction with
M0 to select operating mode.
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11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC1850.PDF ] | |
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