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PDF CY23EP09 Data sheet ( Hoja de datos )
| Número de pieza | CY23EP09 | |
| Descripción | 9-Output Zero Delay Buffer | |
| Fabricantes | Cypress Semiconductor | |
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CY23EP09
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output
Zero Delay Buffer
Features
Functional Description
• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by
loading on CLKOUT pin
• Multiple low-skew outputs
— 45 ps typical output-output skew
— One input drives nine outputs, grouped as 4 + 4 + 1
• 25 ps typical cycle-to-cycle jitter
• 15 ps typical period jitter
• Standard and High drive strength options
• Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages
• 3.3V or 2.5V operation
• Industrial temperature available
The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed
to distribute high-speed clocks and is available in a 16-pin
SOIC or TSSOP package. The -1H version operates up to 220
(200) MHz frequencies at 3.3V (2.5V), and has higher drive
than the -1 devices. All parts have on-chip PLLs that lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
There are two banks of four outputs each, which can be
controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The PLL enters a power-down mode when there are no rising
edges on the REF input (less than ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25 µA of current draw.
In the special case when S2:S1 is 1:0, the PLL is bypassed
and REF is output from DC to the maximum allowable
frequency. The part behaves like a non-zero delay buffer in this
mode, and the outputs are not tri-stated.
The CY23EP09 is available in different configurations, as
shown in the Ordering Information table. The CY23EP09-1 is
the base part. The CY23EP09-1H is the high-drive version of
the -1, and its rise and fall times are much faster than the -1.
These parts are not intended for 5V input-tolerant applications
Block Diagram
Pin Configuration
REF
S2
S1
PLL MUX
Select Input
Decoding
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07760 Rev. *B
Revised October 5, 2005
1 page  
www.DCaYtaS2h3eeEt4PU.c0o9m
3.3V and 2.5V AC Electrical Specifications (continued)
Parameter
tLOCK
TJCC[9,10]
Description
PLL Lock Time[9]
Cycle-to-cycle Jitter, Peak
Test Conditions
Stable power supply, valid clocks presented on
REF and CLKOUT pins
3.3V supply, >66 MHz, <15 pF
3.3V supply, >66 MHz, <30 pF, standard drive
Min.
–
–
–
Typ.
–
25
65
Max.
1.0
55
125
Unit
ms
ps
ps
3.3V supply, >66 MHz, <30 pF, high drive
– 53 100 ps
2.5V supply, >66 MHz, <15 pF, standard drive – 35 95 ps
2.5V supply, >66 MHz, <15 pF, high drive
– 30 65 ps
2.5V supply, >66 MHz, <30 pF, high drive
– 75 145 ps
S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive – 16 – ps
S2:S1 = 1:0 mode, 3.3V, <15pF, high drive
– 14 – ps
S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive – 23 – ps
TPER[9,10] Period Jitter, Peak
S2:S1 = 1:0 mode, 2.5V, <15pF, high drive
3.3V supply, 66–100 MHz, <15 pF
3.3V supply, >100 MHz, <15 pF
– 22 – ps
– 20 75 ps
– 15 45 ps
3.3V supply, >66 MHz, <30 pF, standard drive – 40 100 ps
3.3V supply, >66 MHz, <30 pF, high drive
– 30 70 ps
2.5V supply, >66 MHz, <15 pF, standard drive – 25 60 ps
2.5V supply, 66–100 MHz, <15 pF, high drive
– 25 60 ps
2.5V supply, >100 MHz, <15 pF, high drive
– 15 45 ps
S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive – 28 – ps
S2:S1 = 1:0 mode, 3.3V, <15pF, high drive
– 24 – ps
S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive – 40 – ps
S2:S1 = 1:0 mode, 2.5V, <15pF, high drive
– 37 – ps
Note:
10. Typical jitter is measured at 3.3V or 2.5V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may
be found in the application note “Understanding Data Sheet Jitter Specifications for Cypress Clock Products.”
Switching Waveforms
VDD/2
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
All Outputs Rise/Fall Time
OUTPUT 2.0V(1.8V)
0.8V(0.6V)
t3
2.0V(1.8V)
0.8V(0.6V)
t4
3.3V(2.5V)
0V
Document #: 38-07760 Rev. *B
Page 5 of 13
5 Page 
Ordering Information
Ordering Code
Lead-free
CY23EP09SXC-1
CY23EP09SXC-1T
CY23EP09SXI-1
CY23EP09SXI-1T
CY23EP09SXC-1H
CY23EP09SXC-1HT
CY23EP09SXI-1H
CY23EP09SXI-1HT
CY23EP09ZXC-1H
CY23EP09ZXC-1HT
CY23EP09ZXI-1H
CY23EP09ZXI-1HT
Package Type
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC –
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 150-mil SOIC
16-pin 150-mil SOIC – Tape and Reel
16-pin 4.4-mm TSSOP
16-pin 4.4-mm TSSOP – Tape and Reel
16-pin 4.4-mm TSSOP
16-pin 4.4-mm TSSOP – Tape and Reel
www.DCaYtaS2h3eeEt4PU.c0o9m
Operating Range
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Industrial
Package Drawing and Dimensions
16 Lead (150 Mil) SOIC
81
16-Lead (150-Mil) SOIC S16
PIN 1 ID
DIMENSIONS IN INCHES[MM] MIN.
REFERENCE JEDEC MS-012
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART #
S16.15 STANDARD PKG.
9 16
SZ16.15 LEAD FREE PKG.
MAX.
0.386[9.804]
0.393[9.982]
0.050[1.270]
BSC
0.0138[0.350]
0.0192[0.487]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.004[0.102]
0.0098[0.249]
0° ~8°
0.010[0.254] X 45°
0.016[0.406]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
51-85068-*B
Document #: 38-07760 Rev. *B
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CY23EP09.PDF ] | |
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