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PDF CY23EP05 Data sheet ( Hoja de datos )
| Número de pieza | CY23EP05 | |
| Descripción | 5 Output Zero Delay Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY23EP05
2.5V or 3.3V,10- 220 MHz, Low Jitter, 5 Output
Zero Delay Buffer
Features
Functional Description
• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by
loading on CLKOUT pin
• Multiple low-skew outputs
— 30 ps typical output-output skew
— One input drives five outputs
• 22 ps typical cycle-to-cycle jitter
• 13 ps typical period jitter
• Standard and High drive strength options
• Available in space-saving 150-mil SOIC package
• 3.3V or 2.5V operation
• Industrial temperature available
The CY23EP05 is a 2.5V or 3.3V zero delay buffer designed
to distribute low-jitter high-speed clocks and is available in a
8-pin SOIC package. It accepts one reference input, and
drives out five low-skew clocks. The -1H version operates up
to 220 (200) MHz frequencies at 3.3V (2.5V), and has a higher
drive strength than the -1 devices. All parts have on-chip PLLs
which lock to an input clock on the REF pin. The PLL feedback
is on-chip and is obtained from the CLKOUT pad.
The CY23EP05 PLL enters a power-down mode when there
are no rising edges on the REF input (<~2 MHz). In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 25 µA of current draw.
The CY23EP05 is available in different configurations, as
shown in the Ordering Information table. The CY23EP05-1 is
the base part. The CY23EP05-1H is the high-drive version of
the -1, and its rise and fall times are much faster than the -1.
These parts are not intended for 5V input-tolerant applications
Block Diagram
Pin Configuration
REF PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
Top View
REF
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLK4
VDD
CLK3
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07759 Rev. *B
Revised December 13, 2005
1 page  
www.DCaYtaS2h3eeEt4PU.c0o5m
3.3V and 2.5V AC Electrical Specifications (continued)
Parameter
tLOCK
TJCC[8,9]
Description
PLL Lock Time[8]
Cycle-to-cycle Jitter, Peak
Test Conditions
Stable power supply, valid clocks presented on
REF and CLKOUT pins
3.3V supply, >66 MHz, <15 pF
3.3V supply, >66 MHz, <30 pF, standard drive
3.3V supply, >66 MHz, <30 pF, high drive
2.5V supply, >66 MHz, <15 pF, standard drive
2.5V supply, >66 MHz, <15 pF, high drive
TPER[8,9]
Period Jitter, Peak
2.5V supply, >66 MHz, <30 pF, high drive
3.3V supply, 66–100 MHz, <15 pF
3.3V supply, >100 MHz, <15 pF
3.3V supply, >66 MHz, <30 pF, standard drive
3.3V supply, >66 MHz, <30 pF, high drive
2.5V supply, >66 MHz, <15 pF, standard drive
2.5V supply, 66–100 MHz, <15 pF, high drive
2.5V supply, >100 MHz, <15 pF, high drive
Switching Waveforms
VDD/2
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
Min.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
–
22
45
45
40
35
52
18
13
28
26
25
22
19
Max.
1.0
55
125
100
100
80
125
60
35
75
70
60
60
45
Unit
ms
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
All Outputs Rise/Fall Time
OUTPUT 2.0V(1.8V)
0.8V(0.6V)
2.0V(1.8V)
0.8V(0.6V)
t3 t4
Output-Output Skew
3.3V(2.5V)
0V
OUTPUT
VDD/2
OUTPUT
VDD/2
t5
Note:
9. Typical jitter is measured at 3.3V or 2.5V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be
found in the application notes, “Understanding Data Sheet Jitter Specifications for Cypress Products.”
Document #: 38-07759 Rev. *B
Page 5 of 12
5 Page 
www.DCaYtaS2h3eeEt4PU.c0o5m
Ordering Information
Ordering Code
Lead-free
CY23EP05SXC-1
CY23EP05SXC-1T
CY23EP05SXI-1
CY23EP05SXI-1T
CY23EP05SXC-1H
CY23EP05SXC-1HT
CY23EP05SXI-1H
CY23EP05SXI-1HT
Package Type
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
8-pin 150-mil SOIC
8-pin 150-mil SOIC – Tape and Reel
Operating Range
Commercial
Commercial
Industrial
Industrial
Commercial
Commercial
Industrial
Industrial
Package Drawing and Dimensions
8 Lead (150 Mil) SOIC - S80-8lead (150-Mil) SOIC S8
PIN 1 ID
41
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
58
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
0.189[4.800]
0.196[4.978]
SEATING PLANE
0.010[0.254] X 45°
0.016[0.406]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
51-85066-*C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07759 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY23EP05.PDF ] | |
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