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PDF MAX5898 Data sheet ( Hoja de datos )
| Número de pieza | MAX5898 | |
| Descripción | 16-Bit/ 500Msps Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3756; Rev 1; 7/07
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
General Description
The MAX5898 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high-
performance wideband, single- and multicarrier transmit
applications. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 16-bit, high-speed DACs on a single integrated cir-
cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 81dBc, while only consuming
1.2W. The device also delivers 71dB ACLR for four-
carrier WCDMA at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease recon-
struction filter requirements and enhance the passband
dynamic performance. Each channel includes offset and
gain programmability, allowing the user to calibrate out
local oscillator (LO) feedthrough and sideband suppres-
sion errors generated by analog quadrature modulators.
The MAX5898 features a fIM / 4 digital image-reject
modulator. This modulator generates a quadrature-mod-
ulated IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM / 2 or fIM / 4.
The MAX5898 features a standard LVDS interface for
low electromagnetic interference (EMI). Interleaved
data is applied through a single 16-bit bus. A 3.3V
SPI™ port is provided for mode configuration. The pro-
grammable modes include the selection of 2x/4x/8x
interpolating filters, fIM / 2, fIM / 4 or no digital quadra-
ture modulation with image rejection, individual channel
gain and offset adjustment, and offset binary or two’s-
complement data interface.
Compatible versions with CMOS interfaces and 12-, 14-,
and 16-bit resolutions are also available. Refer to the
MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14-
bit CMOS, and the MAX5895 for 16-bit CMOS versions.
Applications
Base Stations: 3G Multicarrier UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
Features
♦ 71dB ACLR at fOUT = 61.44MHz (Four-Carrier
WCDMA)
♦ Meets Multicarrier UMTS, cdma2000®, GSM
Spectral Masks (fOUT = 122MHz)
♦ Noise Spectral Density = -160dBFS/Hz at
fOUT = 16MHz
♦ 90dBc SFDR at Low-IF Frequency (10MHz)
♦ 88dBc SFDR at High-IF Frequency (50MHz)
♦ Low Power: 831mW (fCLK = 250MHz)
♦ User Programmable
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 95dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM / 2,
or fIM / 4
Selectable Output Filter: Lowpass or Highpass
Per Channel Gain and Offset Adjustment
♦ EV Kit Available (Order the MAX5898EVKIT)
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
PKG
CODE
MAX5898EGK+D
-40°C to +85°C
68 QFN-EP*
(10mm x 10mm)
G6800-4
MAX5898EGK-D
-40°C to +85°C
68 QFN-EP*
(10mm x 10mm)
G6800-4
+Denotes a lead-free package.
D = Dry pack.
*EP = Exposed paddle.
Selector Guide
PART
MAX5893
MAX5894
MAX5895
MAX5898
RESOLUTION
(BITS)
12
14
16
16
DAC UPDATE
RATE (Msps)
500
500
500
500
INPUT
LOGIC
CMOS
CMOS
CMOS
LVDS
Simplified Diagram
DATA PORT
OUTI
DAC
DATACLK
DAC
OUTQ
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Rise/Fall Time
CLOAD = 10pF, 20% to 80%
LVDS LOGIC INPUTS (D15P–D0P, D15N–D0N, SELIQP, SELIQN)
Differential Input Logic High
VIH
Differential Input Logic Low
VIL
Input Common-Mode Voltage
VICM
Differential Input Resistance
RIN
Input Capacitance
CIN
LVDS CLOCK INPUT/OUTPUT (DATACLKP, DATACLKN)
Differential Input Amplitude High
VIH
Differential Input Amplitude Low
VIL
Differential Output Amplitude High
Differential Output Amplitude Low
VOH
VOL
RLOAD = 100Ω differential (Note 3)
RLOAD = 100Ω differential (Note 3)
Output Common-Mode Voltage
VOCM
Output Rise/Fall Time
RLOAD = 100Ω differential, CLOAD = 8pF,
20% to 80%
1.5
100
-100
1.125 1.25 1.375
110
2.5
250
-250
250 340
-340 -250
1.25
0.9
ns
mV
mV
V
Ω
pF
mV
mV
mV
mV
V
ns
CLOCK INPUTS (CLKP, CLKN) (Note 8)
Differential Input Voltage Swing
Differential Input Slew Rate
VDIFF
Sine-wave input
Square-wave input
> 1.5
> 0.5
> 100
VP-P
V/µs
Common-Mode Voltage
VCOM AC-coupled
AVCLK /
2
V
Differential Input Resistance
RCLK
Differential Input Capacitance
CCLK
Minimum Clock Duty Cycle
Maximum Clock Duty Cycle
CLKP/CLKN, DATACLK TIMING (Figure 4) (Note 9)
CLK to DATACLK Delay
tD DATACLK output mode
Data Hold Time
tDH
Data Setup Time
tDS
SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 9)
SCLK Frequency
CS Setup Time
fSCLK
tSS
Input Hold Time
tSDH
Input Setup Time
tSDS
Data Valid Duration
tSDV
POWER SUPPLIES
5 kΩ
5 pF
45 %
55 %
1.65
-0.65
1.4
ns
ns
ns
10 MHz
2.5 ns
0 ns
4.5 ns
6.5 16.5 ns
Digital Supply Voltage
Digital I/O Supply Voltage
DVDD1.8
DVDD3.3
1.71 1.8 1.89
3.0 3.3 3.6
V
V
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
PIN
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53, 67
54, 56, 59, 61,
64, 66
55, 60, 65
57
58
62
63
68
EP
NAME
D3N
D3P
D2N
D2P
D1N
D1P
D0N
D0P
DVDD3.3
DOUT
DIN
SCLK
CS
RESET
REFIO
DACREF
FSADJ
AVDD1.8
GND
AVDD3.3
OUTQN
OUTQP
OUTIN
OUTIP
AVCLK
GND
Pin Description (continued)
FUNCTION
Complementary LVDS Data Bit 3. Internal 110Ω termination to D3P.
LVDS Data Bit 3. Internal 110Ω termination to D3N.
Complementary LVDS Data Bit 2. Internal 110Ω termination to D2P.
LVDS Data Bit 2. Internal 110Ω termination to D2N.
Complementary LVDS Data Bit 1. Internal 110Ω termination to D1P.
LVDS Data Bit 1. Internal 110Ω termination to D1N.
Complementary LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0P.
LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0N.
I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass with a 0.1µF capacitor as close to
the pin as possible.
Serial-Port Data Output
Serial-Port Data Input
Serial-Port Clock Input. Data on DIN is latched on the rising edge of SCLK.
Serial-Port Interface Select. Drive CS low to enable serial-port interface.
Reset Input. Hold RESET low during power-up.
Reference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.
Current-Set Resistor Return Path. For a 20mA full-scale output current, use a 1.25V external reference
and connect a 2kΩ resistor between FSADJ and DACREF. Internally connected to GND. DO NOT USE
AS AN EXTERNAL GROUND CONNECTION.
Full-Scale Adjust Input. For a 20mA full-scale output current, use a 1.25V external reference and
connect a 2kΩ resistor between FSADJ and DACREF.
Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.
Ground
Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1µF capacitor as close to the pin as possible.
Inverting Differential DAC Current Output for Q Channel
Noninverting Differential DAC Current Output for Q Channel
Inverting Differential DAC Current Output for I Channel
Noninverting Differential DAC Current Output for I Channel
Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.
Exposed Paddle. Must be connected to GND through a low-impedance path.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX5898.PDF ] | |
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