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PDF MAX5895 Data sheet ( Hoja de datos )

Número de pieza MAX5895
Descripción 16-Bit/ 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
Fabricantes Maxim Integrated Products 
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No Preview Available ! MAX5895 Hoja de datos, Descripción, Manual

19-3545; Rev 2; 10/08
EVAALVUAAILTAIOBNLEKIT
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16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
General Description
The MAX5895 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for
high-performance, wideband single- and multicarrier
transmit applications. The device integrates a selectable
2x/4x/8x interpolating filter, a digital quadrature modula-
tor, and dual 16-bit high-speed DACs on a single IC. At
30MHz output frequency and 500Msps update rate, the
in-band SFDR is 88dBc while consuming 1.1W. The
device also delivers 71dB ACLR for four-carrier WCDMA
at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease
reconstruction filter requirements and enhance the
passband dynamic performance. Individual offset and
gain programmability allow the user to calibrate out local
oscillator (LO) feedthrough and sideband suppression
errors generated by analog quadrature modulators.
The MAX5895 features a fIM/4 digital image-reject mod-
ulator. This modulator generates a quadrature-modulat-
ed IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM/2 or fIM/4.
The MAX5895 features a standard 1.8V CMOS, 3.3V tol-
erant data input bus for easy interface. A 3.3V SPI™ port
is provided for mode configuration. The programmable
modes include the selection of 2x/4x/8x interpolating fil-
ters, fIM/2, fIM/4 or no digital quadrature modulation with
image rejection, channel gain and offset adjustment, and
offset binary or two’s complement data interface.
Pin-compatible 12- and 14-bit devices are also available.
Refer to the MAX5894 data sheet for the 14-bit version
and the MAX5893 data sheet for the 12-bit version.
Applications
Base Stations: 3G Multicarrier UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
Pin Configuration appears at end of data sheet.
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of the Telecommunications
Industry Association.
Features
o 71dB ACLR at fOUT = 61.44MHz (Four-Carrier
WCDMA)
o Meets Multicarrier UMTS, cdma2000®, GSM
Spectral Masks (fOUT = 122MHz)
o Noise Spectral Density = -158dBFS/Hz at
fOUT = 16MHz
o 92dBc SFDR at Low-IF Frequency (10MHz)
o 90dBc SFDR at High-IF Frequency (50MHz)
o Low Power: 511mW (fCLK = 100MHz)
o User Programmable
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 99dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM/2, or
fIM/4
Selectable Output Filter: Lowpass or Highpass
Channel Gain and Offset Adjustment
o EV Kit Available (Order the MAX5895 EV Kit)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5895EGK-D
-40°C to +85°C
68 QFN-EP*
MAX5895EGK+D
-40°C to +85°C
68 QFN-EP*
D = Dry pack.
*EP = Exposed pad.
+Denotes a lead-free/RoHS-compliant package.
Selector Guide
PART
MAX5893
MAX5894
MAX5895
MAX5898
RESOLUTION
(BITS)
12
14
16
16
DAC UPDATE
RATE (Msps)
500
500
500
500
INPUT
LOGIC
CMOS
CMOS
CMOS
LVDS
Simplified Diagram
DATA
PORT A
DATACLK
DATA
PORT B
OUTI
DAC
DAC
OUTQ
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

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MAX5895 pdf
www.DataSheet4U.com
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50double-terminated outputs, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are
at TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output High Voltage
VOH 200µA load
0.8 x
DVDD3.3
V
Output Low Voltage
VOL 200µA load
Output Leakage Current
Three-state
Rise/Fall Time
CLOAD = 10pF, 20% to 80%
CLOCK INPUT (CLKP, CLKN)
Differential Input Voltage Swing
VDIFF
Sine-wave input
Square-wave input
Differential Input Slew Rate
Common-Mode Voltage
Input Resistance
VCOM
RCLK
AC-coupled
Input Capacitance
CCLK
Minimum Clock Duty Cycle
Maximum Clock Duty Cycle
CLKP/CLKN, DATACLK TIMING (Figure 4, Notes 7, 8)
CLK to DATACLK Delay
Data Hold Time, DATACLK
Input/Output (Pin 14)
tD DATACLK output mode, CLOAD = 10pF
Capturing rising edge
tDH Capturing falling edge
Data Setup Time, DATACLK
Input/Output (Pin 14)
Capturing rising edge
tDS Capturing falling edge
Data Hold Time, DATACLK/B14
Input/Output (Pin 27)
Capturing rising edge
tDH Capturing falling edge
Data Setup Time, DATACLK/B14
Input/Output (Pin 27)
Capturing rising edge
tDS Capturing falling edge
SERIAL-PORT INTERFACE TIMING (Figure 3, Note 7)
SCLK Frequency
CS Setup Time
Input Hold Time
Input Setup Time
fSCLK
tSS
tSDH
tSDS
Data Valid Duration
tSDV
0.2 x
DVDD3.3
V
1 µA
1.5 ns
> 1.5
> 0.5
> 100
AVCLK/2
5
3
45
55
VP-P
V/µs
V
k
pF
%
%
6.2
1.0
2.1
0.4
-0.7
1.0
2.3
0.2
-0.4
ns
ns
ns
ns
ns
10 MHz
2.5 ns
0 ns
4.5 ns
6.5 16.5 ns
_______________________________________________________________________________________ 5

5 Page





MAX5895 arduino
www.DataSheet4U.com
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
PIN
53, 67
54, 56, 59, 61,
64, 66
55, 60, 65
57
58
62
63
68
NAME
AVDD1.8
GND
AVDD3.3
OUTQN
OUTQP
OUTIN
OUTIP
AVCLK
EP
Pin Description (continued)
FUNCTION
Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.
Ground
Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1µF capacitor as close to the pin as possible.
Inverting Differential DAC Current Output for Q-Channel
Noninverting Differential DAC Current Output for Q-Channel
Inverting Differential DAC Current Output for I-Channel
Noninverting Differential DAC Current Output for I-Channel
Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.
Exposed Pad. Must be connected to GND through a low-impedance path.
Functional Diagram
A0–A15
DATACLK
B0–B15
SELIQ
RESET
/2 /2
CONTROL REGISTERS
SERIAL INTERFACE
SDO SDI
CS SCLK
MODULATOR
IQ
fIM/2, fIM/4
IQ
REFERENCE
DACREF FSADJ REFIO
DIGITAL
OFFSET
ADJUST
DIGITAL
GAIN
ADJUST
OUTIP
IDAC
OUTIN
fDAC
MAX5895
DIGITAL
OFFSET
ADJUST
DIGITAL
GAIN
ADJUST
QDAC
OUTQP
OUTQN
/2 /2
fCLK
CLOCK BUFFERS
AND DIVIDERS
CLKN CLKP
fDAC
______________________________________________________________________________________ 11

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