|
|
PDF MAX5891 Data sheet ( Hoja de datos )
| Número de pieza | MAX5891 | |
| Descripción | 16-Bit/ 600Msps -High-Dynamic-Performance/DAC with LVDS Inputs | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAX5891 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
19-3542; Rev 0; 2/05
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
General Description
The MAX5891 advanced 16-bit, 600Msps, digital-to-
analog converter (DAC) meets the demanding perfor-
mance requirements of signal synthesis applications
found in wireless base stations and other communica-
tions applications. Operating from +3.3V and +1.8V
supplies, the MAX5891 DAC supports update rates of
600Msps using high-speed LVDS inputs while consum-
ing only 298mW of power and offers exceptional
dynamic performance such as 80dBc spurious-free
dynamic range (SFDR) at fOUT = 30MHz.
The MAX5891 utilizes a current-steering architecture that
supports a 2mA to 20mA full-scale output current range,
and produces -2dBm to -22dBm full-scale output signal
levels with a double-terminated 50Ω load. The MAX5891
features an integrated +1.2V bandgap reference and
control amplifier to ensure high-accuracy and low-noise
performance. A separate reference input (REFIO) allows
for the use of an external reference source for optimum
flexibility and improved gain accuracy.
The MAX5891 digital inputs accept LVDS voltage lev-
els, and the flexible clock input can be driven differen-
tially or single-ended, AC- or DC-coupled. The
MAX5891 is available in a 68-pin QFN package with an
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
Refer to the MAX5890* and MAX5889* data sheets for
pin-compatible 14-bit and 12-bit versions of the
MAX5891.
Applications
Base Stations: Single/Multicarrier UMTS,
CDMA, GSM
Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Selector Guide
PART
RESOLUTION
(BITS)
UPDATE RATE
(Msps)
LOGIC INPUT
MAX5889*
12
600 LVDS
MAX5890*
14
600 LVDS
MAX5891
16
600
*Future product—contact factory for availability.
LVDS
Features
♦ 600Msps Output Update Rate
♦ Low Noise Spectral Density: -163dBFS/Hz at
fOUT = 36MHz
♦ Excellent SFDR and IMD Performance
SFDR = 80dBc at fOUT = 30MHz (to Nyquist)
SFDR = 69dBc at fOUT = 130MHz (to Nyquist)
IMD = -94dBc at fOUT = 30MHz
IMD = -77dBc at fOUT = 130MHz
♦ ACLR = 73dB at fOUT = 122.88MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ LVDS-Compatible Digital Inputs
♦ On-Chip +1.2V Bandgap Reference
♦ Low 298mW Power Dissipation at 600Msps
♦ Compact (10mm x 10mm) QFN-EP Package
♦ Evaluation Kit Available (MAX5891EVKIT)
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX5891EGK -40°C to +85°C 68 QFN-EP**
**EP = Exposed paddle.
PKG
CODE
G6800-4
Functional Diagram
D0–D15
LVDS DATA
INPUTS
LVDS
RECEIVER
LATCH
MAX5891
OUTP
600MHz
16-BIT DAC
OUTN
CLKP
CLKN
CLK
INTERFACE
+1.2V
REFERENCE
DACREF
REFIO
FSADJ
POWER
DOWN
PD
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference VREFIO = +1.2V, output load 50Ω double-ter-
minated, transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are
guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at
TA = +25°C.)
PARAMETER
Minimum Common-Mode Voltage
Maximum Common-Mode
Voltage
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
Clock Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Clock Supply Current
Digital Supply Current
Total Power Dissipation
Power-Supply Rejection Ratio
SYMBOL
CONDITIONS
RCLK
CCLK
Single-ended
AVDD3.3
AVDD1.8
AVCLK
DVDD3.3
DVDD1.8
IAVDD3.3
IAVDD1.8
IAVCLK
IDVDD3.3
IDVDD1.8
PDISS
PSRR
fCLK = 100MHz, fOUT = 16MHz
fCLK = 500MHz, fOUT = 16MHz
fCLK = 600MHz, fOUT = 16MHz
fCLK = 100MHz, fOUT = 16MHz
fCLK = 500MHz, fOUT = 16MHz
fCLK = 600MHz, fOUT = 16MHz
fCLK = 100MHz, fOUT = 16MHz
fCLK = 500MHz, fOUT = 16MHz
fCLK = 600MHz, fOUT = 16MHz
fCLK = 100MHz, fOUT = 16MHz
fCLK = 500MHz, fOUT = 16MHz
fCLK = 600MHz, fOUT = 16MHz
fCLK = 100MHz, fOUT = 16MHz
fCLK = 500MHz, fOUT = 16MHz
fCLK = 600MHz, fOUT = 16MHz
fCLK = 100MHz, fOUT = 16MHz
fCLK = 500MHz, fOUT = 16MHz
fCLK = 600MHz, fOUT = 16MHz
Power-down, clock static low,
data input static
(Note 5)
MIN TYP MAX UNITS
1V
1.9 V
5 kΩ
3 pF
3.135
1.710
3.135
3.135
1.710
3.3
1.8
3.3
3.3
1.8
26.5
26.5
26.5
11.3
50
61
2.8
2.8
2.8
0.2
0.2
0.2
10.6
44
50.5
137
267
298
3.465
1.890
3.465
3.465
1.890
28
58
3.6
0.5
50
301
13
±0.025
V
V
V
mA
mA
mA
mW
µW
%FS
Note 2: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5891.
Note 3: Parameter measured single-ended with 50Ω double-terminated outputs.
Note 4: Not production tested. Guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltages.
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
16-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Applications Information
Clock Interface
To achieve the best possible jitter performance, the
MAX5891 features flexible differential clock inputs
(CLKP, CLKN) that operate from a separate clock
power supply (AVCLK). Use a low-jitter clock to reduce
the DAC’s phase noise and wideband noise. To
achieve the best DAC dynamic performance, the
CLKP/CLKN input source must be designed carefully.
The differential clock (CLKN and CLKP) input can be
driven from a single-ended or a differential clock
source. Use differential clock drive to achieve the best
dynamic performance from the DAC. For single-ended
operation, drive CLKP with a low noise source and
bypass CLKN to CGND with a 0.1µF capacitor.
Figure 4 shows a convenient and quick way of applying
a differential signal created from a single-ended source
using a wideband transformer. Alternatively, drive
CLKP/CLKN from a CMOS-compatible clock source.
Use sinewave or AC-coupled differential ECL/PECL
drive for best dynamic performance.
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED-TO-
DIFFERENTIAL CONVERSION
SINGLE-ENDED 1:1
CLOCK SOURCE
0.1µF
CLKP
25Ω
TO DAC
25Ω
0.1µF
CLKN
Differential Output Coupling Using a
Wideband RF Transformer
Use a pair of transformers (Figure 5) or a differential
amplifier configuration to convert the differential voltage
existing between OUTP and OUTN to a single-ended
voltage. Optimize the dynamic performance by using a
differential transformer-coupled output and limit the out-
put power to <0dBm full scale. To achieve the best
dynamic performance, use the differential transformer
configuration. Terminate the DAC as shown in Figure 5,
and use 50Ω termination at the transformer single-
ended output. This will provide double 50Ω termination
for the DAC output network. With the double-terminated
output and 20mA full-scale current, the DAC will pro-
duce a full-scale signal level of approximately -2dBm.
Pay close attention to the transformer core saturation
characteristics when selecting a transformer for the
MAX5891. Transformer core saturation can introduce
strong 2nd-order harmonic distortion especially at low
output frequencies and high signal amplitudes. For best
results, connect the center tap of the transformer to
ground. When not using a transformer, terminate each
DAC output to ground with a 25Ω resistor. Additionally,
place a 50Ω resistor between the outputs (Figure 6).
For a single-ended unipolar output, select OUTP as the
output and connect OUTN to AGND. Operating the
MAX5891 single-ended is not recommended because
it degrades the dynamic performance.
The distortion performance of the DAC depends on the
load impedance. The MAX5891 is optimized for 50Ω
differential double termination. Using higher termination
impedance degrades distortion performance and
increases output noise voltage.
AGND
Figure 4. Differential Clock-Signal Generation
D0–D15
LVDS
DATA INPUTS
OUTP
MAX5891
OUTN
AGND
50Ω
100Ω
T1, 1:1
50Ω
Figure 5. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer
T2, 1:1 VOUT, SINGLE-ENDED
WIDEBAND RF TRANSFORMER T2 PERFORMS THE
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MAX5891.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAX5891 | 16-Bit/ 600Msps -High-Dynamic-Performance/DAC with LVDS Inputs | Maxim Integrated Products |
| MAX5893 | 12-Bit/ 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs | Maxim Integrated Products |
| MAX5894 | 14-Bit/ 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs | Maxim Integrated Products |
| MAX5895 | 16-Bit/ 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs | Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |