PDF ADG3304 Data sheet ( Hoja de datos )

Número de pieza	ADG3304
Descripción	Bidirectional Logic Level Translator
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Low Voltage, 1.15 V to 5.5 V, 4-Channel, Bidirectional Logic Level Translator ADG3304 FEATURES Bidirectional level translation Operates from 1.15 V to 5.5 V Low quiescent current < 5 µA No direction pin Qualified for automotive applications APPLICATIONS SPI, MICROWIRE level translation Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces GENERAL DESCRIPTION The ADG3304 is a bidirectional logic level translator that con- tains four bidirectional channels. It can be used in multivoltage digital system applications, such as data transfer, between a low voltage digital signal processing controller and a higher voltage device using SPI and MICROWIRE interfaces. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place. The voltage applied to VCCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA-com- patible logic signals applied to the A side of the device appear as VCCY-compatible levels on the Y side. Similarly, VCCY-compatible logic levels applied to the Y side of the device appear as VCCA- compatible logic levels on the A side. FUNCTIONAL BLOCK DIAGRAM VCCA VCCY A1 Y1 A2 Y2 A3 Y3 A4 Y4 EN GND Figure 1. The enable pin (EN) provides three-state operation on both the A side and the Y side pins. When the EN pin is pulled low, the terminals on both sides of the device are in the high impedance state. The EN pin is referred to the VCCA supply voltage and driven high for normal operation. The ADG3304 is available in compact 14-lead TSSOP, 12-ball WLCSP, and 20-lead LFCSP. It is guaranteed to operate over the 1.15 V to 5.5 V supply voltage range. PRODUCT HIGHLIGHTS 1. Bidirectional level translation. 2. Fully guaranteed over the 1.15 V to 5.5 V supply range. 3. No direction pin. 4. Available in 14-lead TSSOP, 12-ball WLCSP, and 20-lead LFCSP. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADG3304 Data Sheet Parameter SWITCHING CHARACTERISTICS2 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol Test Conditions/Comments tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A RS = RT = 50 Ω, CL = 50 pF, see Figure 37 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A RS = RT = 50 Ω, CL = 50 pF, see Figure 37 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A RS = RT = 50 Ω, CL = 50 pF, see Figure 37 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 Min 50 50 50 50 40 40 B Version1 Typ Max 6 10 2 3.5 2 3.5 24 3 47 13 37 2 3.5 2 8 11 25 25 24 4 58 2 3.5 2 3.5 23 3 9 18 35 25 25 10 59 24 24 24 4 Unit ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns ns ns ns Mbps ns ns Rev. E \| Page 4 of 21 5 Page ADG3304 9 TA = 25°C 1 CHANNEL 8 VCCA = 1.8V VCCY = 3.3V 7 6 5 4 3 2 1 0 13 23 50Mbps 30Mbps 20Mbps 10Mbps 33 43 53 CAPACITIVE LOAD (pF) 5Mbps 63 73 Figure 11. ICCY vs. Capacitive Load at Pin Y for A→Y (1.8 V→3.3 V) Level Translation 5.0 TA = 25°C 4.5 1 CHANNEL VCCA = 1.8V 4.0 VCCY = 3.3V 3.5 3.0 50Mbps 2.5 2.0 30Mbps 1.5 20Mbps 1.0 10Mbps 0.5 0 5Mbps 13 23 33 43 53 CAPACITIVE LOAD (pF) Figure 12. ICCA vs. Capacitive Load at Pin A for Y→A (3.3 V→1.8 V) Level Translation 12 TA = 25°C 1 CHANNEL 10 VCCA = 3.3V VCCY = 5V 50Mbps 8 30Mbps 6 20Mbps 4 10Mbps 2 5Mbps 0 13 23 33 43 53 63 73 CAPACITIVE LOAD (pF) Figure 13. ICCY vs. Capacitive Load at Pin Y for A→Y (3.3 V→5 V) Level Translation Data Sheet 7 TA = 25°C 1 CHANNEL 6 VCCA = 3.3V VCCY = 5V 5 50Mbps 4 30Mbps 3 20Mbps 2 10Mbps 1 5Mbps 0 13 23 33 43 53 CAPACITIVE LOAD (pF) Figure 14. ICCA vs. Capacitive Load at Pin A for Y→A (5 V→3.3 V) Level Translation 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 VCCA = 1.2V, VCCY = 1.8V 7 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 2 VCCA = 3.3V, VCCY = 5V 1 0 13 23 33 43 53 63 73 CAPACITIVE LOAD (pF) Figure 15. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation) 4.0 TA = 25°C 1 CHANNEL 3.5 DATA RATE = 50kbps 3.0 VCCA = 1.2V, VCCY = 1.8V 2.5 VCCA = 1.8V, VCCY = 3.3V 2.0 1.5 VCCA = 3.3V, VCCY = 5V 1.0 0.5 0 13 23 33 43 53 63 73 CAPACITIVE LOAD (pF) Figure 16. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation) Rev. E \| Page 10 of 21 11 Page

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