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PDF CY25823 Data sheet ( Hoja de datos )
| Número de pieza | CY25823 | |
| Descripción | CK-SSCD Spread Spectrum Differential Clock Specification | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY25823
CK-SSCD Spread Spectrum Differential Clock
Specification
Features
• 3.3V operation
• 96- and 100-MHz frequency support
• Selectable slew rate control
• 200-ps jitter
• I2C programmability
• 250-µA power-down current
• Lexmark Spread Spectrum for best electromagnetic
interference (EMI) reduction
• 16-pin TSSOP package
Block Diagram
VDD
VDDA
Clock Input
SDATA
SCLK
PWRDWN
Freq.
Divider
M
Logic
Control
ΣPhase
Detector
Charge
Pump
VCO
Post
Dividers
Feedback
DivNider
Modulating
Waveform
PLL
REFOUT
CLKOUT
(SSCG Output)
CLKOUT#
Pin Configuration
VSS
VSSA
CLKIN
S3
S2
S1
PW RDW N
REFOUT/SEL
SCLK
SDATA
1
2
3
4
5
6
7
8
16 VDDA
15 VSSA
14 IREF
13 VSSIREF
12 CLKOUT
11 CLKOUT#
10 VSS
9 VDD
16 pin TSSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07579 Rev. *C
Revised September 02, 2004
1 page  
www.DatCaSYhe2et54U8.c2o3m
Byte1[7:2] Control Register
Bit @Pup
70
60
50
40
30
21
Pin#
11,12
CLKEN
Name
Pin Description
Reserved set equal to ‘0’
Reserved set equal to ‘0’
Reserved set equal to ‘0’
Reserved set equal to ‘0’
Reserved set equal to ‘0’
CLKOUT/CLKOUT# enable
0 =Disable, 1 = Enable
Byte 1: [1:0] Control Register (Charge Pump Settings)
Bit @Pup
10
00
Default Value
0
0
One Step Higher Than Default
1
1
Two Steps Higher Than Default
1
0
Bytes 2 through 5: Reserved Registers
Byte 6: Vendor/Revision ID Register
Bit @Pup
70
60
50
40
31
20
10
00
Pin#
–
–
–
–
–
–
–
–
Name
–
–
–
–
–
–
–
–
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Pin Description
Spread Enable and Spread Select[3:0]
Spread Enable and Spread Select[3:0] register bits are used
to enable and disable spread spectrum on CLKOUT and to
change the spread modulation. When the spread selection
changes, the CLKOUT output transits to the target spread
selection without deviating from clock specifications.
At device power-up spread spectrum is enabled and hardware
control mode is enabled. The initial spread-spectrum configu-
ration is determined by the S[3:1] pins, which correspond to
the S[3:1] bits in Table 4. The S0 configuration bit is
hard-coded to zero when hardware control mode is selected.
All four spread spectrum configuration bits, S[3:0], can also be
set when the device is in the software control mode.
Charge Pump Select Byte1 [1:0]
Programming these bits (Byte1[1:0]) via I2C enables the user
to have more spread percentage options as described in
Table 5. At the start up the default value for byte1[1:0] bits is
set to ‘00’, this value can be changed via I2C to have higher
spread percentage on CLKOUT and CLKOUT#. Setting the
byte[1:0] bits to ‘11’ allows the user to have a slightly higher
spread percentage than the default value(00). The ‘01’ option
is the highest spread option for maximum EMI reduction.
PWRDWN (Power-down) Clarification
The PWRDWN (Power-down) pin is used to shut off the clock
prior to shutting off power to the device. PWRDWN is an
asynchronous active HIGH input. This signal is synchronized
internally to the device powering down the clock synthesizer.
PWRDWN also is an asynchronous function for powering up
the system. When PWRDWN is high, all clocks are tri-stated
and the oscillator and PLL are also powered down. All clocks
are shut down in a synchronous manner so has not to cause
glitches while transitioning to the stopped state. The CLKIN
input must be on and within specified operating parameters
before PWRDWN is asserted and it must remain in this state
while PWRDWN is asserted, see Figure 1.
When PWRDWN is de-asserted (CLKIN starts after
powerdown de-assertion to meet the IDD≤250µA specifi-
cation) the clocks should remain stopped until the VCO is
stable and within specification (tSTABLE)., see Figure 2.
Document #: 38-07579 Rev. *C
Page 5 of 12
5 Page 
Package Drawing and Dimension
16-lead TSSOP 4.40 MM Body Z16.173
www.DatCaSYhe2e5t4U8.c2o3m
0.65[0.025]
BSC.
0.85[0.033]
0.95[0.037]
PIN 1 ID
1
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
16
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05 gms
PART #
Z16.173 STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
0.076[0.003]
SEATING
PLANE
0.25[0.010]
BSC
GAUGE
PLANE
0° -8°
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07579 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY25823.PDF ] | |
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