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PDF AS1156 Data sheet ( Hoja de datos )
| Número de pieza | AS1156 | |
| Descripción | Single/Dual LVDS Driver | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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AS1156/AS1154
Single/Dual LVDS Driver
Data Sheet
1 General Description
The AS1156/AS1154 is a Single/Dual Flow-Through
LVDS (Low-Voltage Differential Signaling) Line Driver
which accepts and converts LVTTL/LVCMOS input lev-
els into LVDS output signals. The device is perfect for
low-power low-noise applications requiring high signal-
ing rates and reduced EMI emissions.
The device is guaranteed to transmit data at speeds up
to 800Mbps (400MHz) over controlled impedance media
of approximately 100Ω. Supported transmission media
are PCB traces, backplanes, and cables.
The AS1156 is a single LVDS transmitter, and the
AS1154 is a dual LVDS transmitter.
Outputs conform to the ANSI TIA/EIA-644 LVDS stan-
dards. Flow-through pinout simplifies PC board layout
and reduces crosstalk by separating the LVTTL/LVC-
MOS inputs and LVDS outputs.
The AS1156/AS1154 operates from a single +3.3V sup-
ply and is specified for operation from -40 to +85°C.
2 Key Features
Flow-Through Pinout
Guaranteed 800Mbps Data Rate
250ps Pulse Skew (Max)
Conforms to ANSI TIA/EIA-644 LVDS Standards
Single +3.3V Supply
Operating Temperature Range: -40 to +85°C
8-Pin SOIC Package
3 Applications
Digital Copiers, Laser Printers, Cellular Phone Base Sta-
tions, Add/Drop Muxes, Digital Cross-Connects,
DSLAMs, Network Switches/Routers, Backplane Inter-
connect, Clock Distribution Computers, Intelligent Instru-
ments, Controllers, Critical Microprocessors and
Microcontrollers, Power Monitoring, and Portable/Bat-
tery-Powered Equipment.
Figure 1. Block Diagram
AS1156
VCC
Tx
IN1
OUT1-
OUT1+
N/C
GND
N/C
N/C
AS1154
VCC
IN1
Tx
OUT1-
OUT1+
IN2
GND
Tx
OUT2+
OUT2-
www.austriamicrosystems.com
Revision 1.01
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1 page  
AS1156/AS1154
Data Sheet - Electrical Characteristics
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Switching Characteristics
(VCC = +3.0 to +3.6V, RL = 100Ω ±1%, CL = 2.5pF (differential), TA = -40 to +85°C
Typical values are at VCC = +3.3V, TA = +25ºC, Unless Otherwise Noted.) 1, 2, 3, 10
Table 4. Switching Characteristics
Parameter
Symbol
Conditions
Differential Propagation Delay,
High-to-Low
tPHLD
Figure 20 on page 11 and
Figure 21 on page 11
Differential Propagation Delay,
Low-to-High
tPLHD
Figure 20 on page 11 and
Figure 21 on page 11
Differential Pulse Skew 4
tSKD1
Figure 20 on page 11 and
Figure 21 on page 11
Differential Channel-to-Channel Skew 5 tSKD2
Figure 20 on page 11 and
Figure 21 on page 11
Differential Part-to-Part Skew 6
tSKD3
Figure 20 on page 11 and
Figure 21 on page 11
Differential Part-to-Part Skew 7
tSKD4
Figure 20 on page 11 and
Figure 21 on page 11
Rise Time
tTLH
Figure 20 on page 11 and
Figure 21 on page 11
Fall Time
tTHL
Figure 20 on page 11 and
Figure 21 on page 11
Maximum Operating Frequency 8, 9
fMAX
Min Typ Max
1.1 1.268 1.5
1.1 1.267 1.5
90 200
110 250
750
900
200 356 800
200 352 800
400
Unit
ns
ns
ps
ps
ps
ps
ps
ps
MHz
Notes:
1. Parameters are guaranteed by design and characterization.
2. CL includes probe and jig capacitance.
3. Signal generator conditions for dynamic tests: VOL = 0, VOH = 2.4V, f = 100MHz, 50% duty cycle, RO = 50Ω,
tR ≤ 1ns, tF ≤ 1ns (0 to 100%).
4. tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|.
5. tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on
the same device.
6. tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and
within 5°C of each other.
7. tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the
rated supply and temperature ranges.
8. fMAX signal generator conditions: VOL = 0, VOH = 2.4V, 50% duty cycle, RO = 50Ω,
tR ≤ 1ns, tF ≤ 1ns (0 to 100%).
9. Transmitter output criteria: duty cycle = 45 to 55%, VOD ≥ 250mV.
10. For optimum performance matched circuits should be used.
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Revision 1.01
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5 Page 
AS1156/AS1154
Data Sheet - Applications
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Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 20. Driver Propagation Delay and Transition Time Waveforms
INx
OUTx-
OUTx+
1.5V
tPLHD
0 Differential
1.5V
tPHLD
0
20%
80%
0
tTLH
80%
VDIFF = (VOUTx+) - (VOUTx-)
00
20%
tTHL
Figure 21. Driver Propagation Delay and Transition Time Test Circuit
VOH
VOL
Generator
50Ω
OUTx+
CL RL
OUTx-
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Revision 1.01
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