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PDF AS1152 Data sheet ( Hoja de datos )
| Número de pieza | AS1152 | |
| Descripción | Quad LVDS Driver | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AS1152 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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AS1152
Quad LVDS Driver
Data Sheet
1 General Description
The AS1152 is a Quad Flow-Through LVDS (Low-Volt-
age Differential Signaling) Line Driver which accepts
and converts LVTTL/LVCMOS input levels into LVDS
output signals. The device is perfect for low-power low-
noise applications requiring high signaling rates and
reduced EMI emissions.
The device is guaranteed to transmit data at speeds up
to 500Mbps (250MHz) over controlled impedance media
of approximately 100Ω. Supported transmission media
are PCB traces, backplanes, and cables.
The AS1152 is capable of setting all four outputs to a
high-impedance state through two Enable Inputs (EN
and ENn – internally pulled down to GND), dropping the
device to an ultra-low-power state of 16mW (typical) dur-
ing high impedance. The Enable Inputs are common to
all four drivers.
Outputs conform to the ANSI TIA/EIA-644 LVDS stan-
dards. Flow-through pinout simplifies PC board layout
and reduces crosstalk by separating the LVTTL/LVC-
MOS inputs and LVDS outputs.
The AS1152 operates from a single +3.3V supply and is
specified for operation from -40 to +85°C.
2 Key Features
! Flow-Through Pinout
! Guaranteed 500Mbps Data Rate (paired with
AS1150)
! 350ps Pulse Skew (Max)
! Conforms to ANSI TIA/EIA-644 LVDS Standards
! Single +3.3V Supply
! Operating Temperature Range: -40 to +85°C
! 16-Pin TSSOP Package
3 Applications
Digital Copiers, Laser Printers, Cellular Phone Base Sta-
tions, Add/Drop Muxes, Digital Cross-Connects,
DSLAMs, Network Switches/Routers, Backplane Inter-
connect, Clock Distribution Computers, Intelligent Instru-
ments, Controllers, Critical Microprocessors and
Microcontrollers, Power Monitoring, and Portable/Bat-
tery-Powered Equipment.
Figure 1. Block Diagram
IN1
IN2
IN3
IN4
VCC
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
OUT4+
OUT4-
EN
ENn
AS1152
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AS1152
Data Sheet
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6 Typical Operating Characteristics
VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 15pF, Tamb = +25ºC, unless otherwise noted
Figure 2. Output High Voltage vs. VCC
1.41
Figure 3. Output Low Voltage vs. VCC
1.08
1.408
1.406
1.404
1.402
VOUT+
VOUT-
1.075
1.07
1.065
VOUT-
VOUT+
1.4
3
3.1 3.2 3.3 3.4 3.5 3.6
Power-Supply Voltage (V)
Figure 4. Output Short-Circuit Current vs. VCC;
VIN = VCC or GND
3.700
3.675
3.650
3.625
3.600
3.575
3.550
3.525
3.500
3
3.1 3.2 3.3 3.4 3.5
Power-Supply Voltage (V)
Figure 6. Differential Output Voltage vs. VCC
3.6
350
345
340
335
330
325
320
3
3.1 3.2 3.3 3.4 3.5 3.6
Power-Supply Voltage (V)
1.06
3
3.1 3.2 3.3 3.4 3.5 3.6
Power-Supply Voltage (V)
Figure 5. Output High-Impedance State Current vs.
VCC; VIN = VCC or GND
30
29
28
27
26
25
24
3
3.1 3.2 3.3 3.4 3.5 3.6
Power-Supply Voltage (V)
Figure 7. Differential Output Voltage vs. Load
Resistor
500
450
400
350
300
250
90
100 110 120 130 140 150
Load Resistor (Ohm)
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AS1152
Data Sheet
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Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
! Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mis-
matches.
! Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
! Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
! Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
! Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
! Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 18. Driver Propagation Delay and Transition Time Waveforms
INx
OUTx-
OUTx+
1.5V
tPLHD
0 Differential
1.5V
tPHLD
0
20%
80%
0
tTLH
80%
VDIFF = (VOUTx+) - (VOUTx-)
0
20%
tTHL
Figure 19. Driver Propagation Delay and Transition Time Test Circuit
VOH
VOL
Generator
INx
50Ω
OUTx+
RL
OUTx-
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AS1152.PDF ] | |
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