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Número de pieza | AS1150 | |
Descripción | Quad LVDS Receivers | |
Fabricantes | austriamicrosystems AG | |
Logotipo | ||
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AS1150, AS1151
Quad LVDS Receivers
Data Sheet
1 General Description
The AS1150 and AS1151 are quad flow-through LVDS
(low-voltage differential signaling) receivers which
accept LVDS differential inputs and convert them to
LVCMOS outputs. The receivers are perfect for low-
power low-noise applications requiring high signaling
rates and reduced EMI emissions.
The devices are guaranteed to receive data at speeds
up to 500Mbps (250MHz) over controlled impedance
media of approximately 100Ω. Supported transmission
media are PCB traces, backplanes, and cables.
The AS1150 uses high impedance inputs and requires
an external termination resistor when used in a point-to-
point connection. The AS1151 features integrated paral-
lel termination resistors (nominally 107Ω), which elimi-
nate the requirement for discrete termination resistors,
and reduce stub lengths.
The integrated failsafe feature sets the output high if the
inputs are open, undriven and terminated, or undriven
and shorted. Enable inputs (EN and ENn – internally
pulled down to GND) control the high-impedance output
and are common to all four receivers. All inputs conform
to the ANSI TIA/EIA- 644 LVDS standards. Flow-through
pinout simplifies PC board layout and reduces crosstalk
by separating the LVDS inputs and LVCMOS outputs.
The devices are available in a 16-pin TSSOP package.
Figure 1. Block Diagrams
VCC
IN1+
IN1-
Rx
OUT1
IN2+
IN2-
Rx
OUT2
IN3+
IN3-
Rx
OUT3
IN4+
IN4-
EN
Rx
OUT4
ENn AS1150
2 Key Features
! Flow-Through Pinout
! Guaranteed 500Mbps Data Rate
! 300ps Pulse Skew (Max)
! Conform to ANSI TIA/EIA-644 LVDS Standards
! Single +3.3V Supply
! Operating Temperature Range: -40 to +85ºC
! Failsafe Circuit
! Integrated Termination (AS1151)
! 16-pin TSSOP Package
3 Applications
The devices are ideal for digital copiers, laser printers,
cellular phone base stations, add/drop muxes, digital
cross-connects, dslams, network switches/routers,
backplane interconnect, clock distribution computers,
intelligent instruments, controllers, critical microproces-
sors and microcontrollers, power monitoring, and porta-
ble/battery-powered equipment.
VCC
IN1+
IN1-
107Ω
Rx
IN2+
IN2-
107Ω
Rx
IN3+
IN3-
107Ω
Rx
IN4+
IN4-
EN
107Ω
Rx
ENn AS1151
OUT1
OUT2
OUT3
OUT4
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1 page AS1150, AS1151
Data Sheet
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6 Typical Operating Characteristics
VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CLOAD = 15pF, TAMB = +25ºC, unless otherwise noted.
Figure 2. Supply Current vs. Frequency
Figure 3. Supply Current vs. Temperature
100 14
90
80
All Channels Switching
70
12
Outputs Low
10
60 8
50 Outputs High
40 6
30
20
10
0
0,01
One Channel Switching
0,1 1 10 100 1000
Frequency (MHz)
4
2
0
-40 -20
0 20 40 60
Tem perature (°C)
80
100
Figure 4. Diff. Threshold Voltage vs. VCC
70
60
High to Low
50
40 Low to High
30
20
10
0
3 3,1 3,2 3,3 3,4 3,5 3,6
Supply Voltage (V)
Figure 5. Output Short-Circuit Current vs. VCC
120
100
80
60
40
20
0
3 3,1 3,2 3,3 3,4 3,5 3,6
Supply Voltage (V)
Figure 6. Output Low Voltage vs. VCC
110
Figure 7. Output High Voltage vs. VCC
3,7
109 3,5
108 3,3
107 3,1
106 2,9
105
3
3,1 3,2 3,3 3,4 3,5 3,6
Supply Voltage (V)
2,7
3
3,1 3,2 3,3 3,4 3,5 3,6
Supply Voltage (V)
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5 Page AS1150, AS1151
Data Sheet
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Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
! Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mis-
matches.
! Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
! Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Termination
Due to the high data rates of LVDS drivers, matched termination will prevent the generation of any signal reflections,
and reduce EMI.
! The AS1151 has integrated termination resistors connected across the inputs of each receiver. The value of the
integrated resistor is specified in Table 2 on page 3.
! The AS1150 requires an external termination resistor. The termination resistor should match the differential imped-
ance of the transmission line and be placed as close to the receiver inputs as possible. Termination resistance val-
ues may range between 90 to 132Ω depending on the characteristic impedance of the transmission medium. Use
1% surface-mount resistors.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
! Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
! Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
! Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
! Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 18. Propagation Delay and Transition Time Test Circuit
Pulse
Generator**
INx+
INx-
OUT
CL
50Ω 50Ω
Receiver Enabled
1/4 AS1150, AS1151
* 50Ω required for pulse generator.
** When testing the AS1151, adjust the pulse generator output
to account for internal termination resistor.
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11 Page |
Páginas | Total 15 Páginas | |
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