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PDF MAX19192 Data sheet ( Hoja de datos )
| Número de pieza | MAX19192 | |
| Descripción | Dual 8-Bit ADC | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-5098; Rev 0; 1/10
www.DataSheet4U.com
Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
General Description
The MAX19192 is an ultra-low-power, dual, 8-bit, 10Msps
analog-to-digital converter (ADC). The device features
two fully differential wideband track-and-hold (T/H)
inputs. These inputs have a 440MHz bandwidth and
accept fully differential or single-ended signals. The
MAX19192 delivers a typical signal-to-noise and distor-
tion (SINAD) of 48.6dB at an input frequency of
1.875MHz and a sampling rate of 10Msps while consum-
ing only 15.3mW. This ADC operates from a 2.7V to 3.6V
analog power supply. A separate 1.8V to 3.6V supply
powers the digital output driver. In addition to ultra-low
operating power, the MAX19192 features three power-
down modes to conserve power during idle periods.
Excellent dynamic performance, ultra-low power, and
small size make the MAX19192 ideal for applications in
imaging, instrumentation, and digital communications.
An internal 1.024V precision bandgap reference sets
the full-scale range of the ADC to ±0.512V. A flexible
reference structure allows the MAX19192 to use its
internal reference or accept an externally applied refer-
ence for applications requiring increased accuracy.
The MAX19192 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output for-
mat is offset binary. A separate digital power input
accepts a voltage from 1.8V to 3.6V for flexible interfac-
ing to different logic levels. The MAX19192 is available
in a 5mm × 5mm, 28-pin thin QFN package, and is
specified for the extended industrial (-40°C to +85°C)
temperature range.
For higher sampling frequency applications, refer to the
MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible
versions of the MAX19192 are also available. Refer to
the MAX1191 data sheet for 7.5Msps, the MAX1192
data sheet for 22Msps, and the MAX1193 data sheet
for 45Msps.
Applications
Ultrasound and Medical Imaging
IQ Baseband Sampling
Battery-Powered Portable Instruments
Low-Power Video
WLAN, Mobile DSL, WLL Receiver
Digital Audio Receiver Front-End
Features
o Ultra-Low Power
15.3mW (Normal Operation: 10Msps)
2µW (Shutdown Mode)
o Excellent Dynamic Performance
48.6dB SNR at fIN = 1.875MHz
70dBc SFDR at fIN = 1.875MHz
o 2.7V to 3.6V Single Analog Supply
o 1.8V to 3.6V TTL/CMOS-Compatible Digital
Outputs
o Fully Differential or Single-Ended Analog Inputs
o Internal/External Reference Option
o Multiplexed CMOS-Compatible Three-State Outputs
o 28-Pin Thin QFN Package
o Evaluation Kit Available (Order MAX19192EVKIT+)
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX19192ETI+
-40°C to +85°C 28 Thin QFN-EP*
MAX19192ETI/V+** -40°C to +85°C 28 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
/V denotes an automotive qualified part.
**Future product—contact factory for availability.
Pin Configuration
TOP VIEW
INA- 1
INA+ 2
GND 3
CLK 4
GND 5
INB+ 6
INB- 7
+
MAX19192
EXPOSED PAD
21 D0
20 D1
19 D2
18 D3
17 A/B
16 D4
15 D5
5mm x 5mm THIN QFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM =
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Normal operating mode,
fIN = 1.875MHz at -0.5dBFS, CL ≈ 10pF 1.6 mA
Digital Output Supply Current
(Note 3)
IODD
Idle mode (three-state), DC input, CLK =
GND or VDD, PD0 = OVDD, PD1 = OGND
Standby mode, DC input, CLK = GND or
VDD, PD0 = OGND, PD1 = OVDD
0.1 5.0
0.1 µA
Shutdown mode, CLK = GND or VDD,
PD0 = PD1 = OGND
0.1 5.0
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
tDOA
50% of CLK to 50% of data, Figure 5
(Note 4)
1 6 8.5 ns
CLK Fall to CHB Output Data
Valid
CLK Rise/Fall to A/B Rise/Fall
Time
PD1 Rise to Output Enable
PD1 Fall to Output Disable
CLK Duty Cycle
CLK Duty-Cycle Variation
Wake-Up Time from Shutdown
Mode
tDOB
tDA/B
tEN
tDIS
50% of CLK to 50% of data, Figure 5
(Note 4)
50% of CLK to 50% of A/B, Figure 5
(Note 4)
PD0 = OVDD
PD0 = OVDD
tWAKE, SD (Note 5)
1 6 8.5 ns
1 6 8.5 ns
5 ns
5 ns
50 %
±10 %
20 µs
Wake-Up Time from Standby
Mode
tWAKE, ST (Note 5)
5.5 µs
Digital Output Rise/Fall Time
20% to 80%
2 ns
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
fIN,X = 1.875MHz at -0.5dBFS,
fIN,Y = 3.0MHz at -0.5dBFS
-75 dB
Amplitude Matching
Phase Matching
fIN = 1.875MHz at -0.5dBFS (Note 6)
fIN = 1.875MHz at -0.5dBFS (Note 6)
±0.03
±0.03
dB
Degrees
Note 1: Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3: The power consumption of the output driver is proportional to the load capacitance (CL).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: SINAD settles to within 0.5dB of its typical value.
Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
_______________________________________________________________________________________ 5
5 Page 
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Ultra-Low-Power, 10Msps, Dual 8-Bit ADC
+
T/H
-
FLASH
ADC
DAC
x2
INA+
T/H
INA-
1.5 BITS
STAGE 1
STAGE 2
STAGE 7
DIGITAL ERROR CORRECTION
D0–D7
Figure 1. Pipeline Architecture—Stage Blocks
Detailed Description
The MAX19192 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for channel A and
5.5 clock cycles for channel B.
At each stage, flash ADCs convert the held input volt-
ages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
original held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeat-
ed until the signal has been processed by all stages.
Digital error correction compensates for ADC compara-
tor offsets in each pipeline stage and ensures no miss-
ing codes. Figure 2 shows the MAX19192 functional
diagram.
INA+
INA-
REFIN
REFP
COM
REFN
INB+
INB-
PIPELINE
T/H ADC / DEC
A
MAX19192 POWER
CONTROL
VDD
GND
PD0
PD1
OVDD
REFERENCE
SYSTEM AND
BIAS
CIRCUITS
MULTIPLEXER
OUTPUT
DRIVERS
D0–D7
A/B
OGND
PIPELINE
T/H ADC / DEC
B
TIMING
CLK
Figure 2. MAX19192 Functional Diagram
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MAX19192.PDF ] | |
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