|
|
PDF MAX19191 Data sheet ( Hoja de datos )
| Número de pieza | MAX19191 | |
| Descripción | 8-Bit ADC | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAX19191 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
19-5099; Rev 0; 1/10
www.DataSheet4U.com
Ultra-Low-Power, 10Msps, 8-Bit ADC
General Description
The MAX19191 is an ultra-low-power, 8-bit, 10Msps
analog-to-digital converter (ADC). The device features
a fully differential wideband track-and-hold (T/H) input.
This input has a 440MHz bandwidth and accepts fully
differential or single-ended signals. The MAX19191
delivers a typical signal-to-noise and distortion (SINAD)
of 48.6dB at an input frequency of 1.875MHz and a
sampling rate of 10Msps while consuming only
15.3mW. This ADC operates from a 2.7V to 3.6V analog
power supply. A separate 1.8V to 3.6V supply powers
the digital output driver. In addition to ultra-low operat-
ing power, the MAX19191 features three power-down
modes to conserve power during idle periods. Excellent
dynamic performance, ultra-low power, and small size
make the MAX19191 ideal for applications in imaging,
instrumentation, and digital communications.
An internal 1.024V precision bandgap reference sets the
full-scale range of the ADC to ±0.512V. A flexible refer-
ence structure allows the MAX19191 to use its internal
reference or accept an externally applied reference for
applications requiring increased accuracy.
The MAX19191 features parallel, CMOS-compatible
three-state outputs. The digital output format is offset
binary. A separate digital power input accepts a voltage
from 1.8V to 3.6V for flexible interfacing to different logic
levels. The MAX19191 is available in a 5mm × 5mm, 28-
pin thin QFN package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
For higher sampling frequency applications, refer to the
MAX1195–MAX1198 dual 8-bit ADCs. For a dual-channel,
pin-compatible version, refer to the MAX19192 data
sheet.
Applications
Ultrasound and Medical Imaging
Battery-Powered Portable Instruments
Low-Power Video
WLAN, Mobile DSL, WLL Receiver
Digital Audio Receiver Front-End
Features
o Ultra-Low Power
15.3mW (Normal Operation: 10Msps)
2µW (Shutdown Mode)
o Excellent Dynamic Performance
48.6dB SNR at fIN = 1.875MHz
70dBc SFDR at fIN = 1.875MHz
o 2.7V to 3.6V Single Analog Supply
o 1.8V to 3.6V TTL/CMOS-Compatible Digital
Outputs
o Fully Differential or Single-Ended Analog Inputs
o Internal/External Reference Option
o Multiplexed CMOS-Compatible Three-State Outputs
o 28-Pin Thin QFN Package
o Evaluation Kit Available (Order MAX19191EVKIT+)
Ordering Information
PART
MAX19191ETI+
MAX19191ETI/V+**
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 Thin QFN-EP*
28 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
/V denotes an automotive qualified part.
**Future product—contact factory for availability.
Pin Configuration
TOP VIEW
IN- 1
IN+ 2
GND 3
CLK 4
GND 5
GND 6
GND 7
+
MAX19191
EXPOSED PAD
21 D0
20 D1
19 D2
18 D3
17 DVAL
16 D4
15 D5
5mm x 5mm THIN QFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
Ultra-Low-Power, 10Msps, 8-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 10MHz, CREFP = CREFN = CCOM =
0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
tDOA
50% of CLK to 50% of data, Figure 5
(Note 4)
CLK Rise/Fall to DVAL Rise/Fall
Time
tD_DVAL
50% of CLK to 50% of DVAL, Figure 5
(Note 4)
PD1 Rise to Output Enable
PD1 Fall to Output Disable
CLK Duty Cycle
tEN PD0 = OVDD
tDIS PD0 = OVDD
CLK Duty-Cycle Variation
Wake-Up Time from Shutdown
Mode
tWAKE, SD (Note 5)
1 6 8.5 ns
1 6 8.5 ns
5 ns
5 ns
50 %
±10 %
20 µs
Wake-Up Time from Standby
Mode
tWAKE, ST (Note 5)
5.5 µs
Digital Output Rise/Fall Time
20% to 80%
2 ns
Note 1: Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3: The power consumption of the output driver is proportional to the load capacitance (CL).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: SINAD settles to within 0.5dB of its typical value.
_______________________________________________________________________________________ 5
5 Page 
www.DataSheet4U.com
Ultra-Low-Power, 10Msps, 8-Bit ADC
+
T/H ∑
-
FLASH
ADC
DAC
x2
IN+
T/H
IN-
1.5 BITS
STAGE 1
STAGE 2
STAGE 7
DIGITAL ERROR CORRECTION
D0–D7
Figure 1. Pipeline Architecture—Stage Blocks
Detailed Description
The MAX19191 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles.
At each stage, flash ADCs convert the held input volt-
ages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
original held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeat-
ed until the signal has been processed by all stages.
Digital error correction compensates for ADC compara-
tor offsets in each pipeline stage and ensures no miss-
ing codes. Figure 2 shows the MAX19191 functional
diagram.
IN+
IN-
REFIN
REFP
COM
REFN
T/H
PIPELINE
ADC
/ DEC
REFERENCE
SYSTEM AND
BIAS
CIRCUITS
MAX19191
POWER
CONTROL
OUTPUT
DRIVERS
TIMING
VDD
GND
PD0
PD1
OVDD
D0–D7
DVAL
OGND
CLK
Figure 2. MAX19191 Functional Diagram
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX19191.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAX19191 | 8-Bit ADC | Maxim Integrated Products |
| MAX19192 | Dual 8-Bit ADC | Maxim Integrated Products |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |