PDF AD9804 Data sheet ( Hoja de datos )

Número de pieza	AD9804
Descripción	Complete 10-Bit 18 MSPS CCD Signal Processor
Fabricantes	Analog Devices
Logotipo
Hay una vista previa y un enlace de descarga de AD9804 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas
No Preview Available ! a FEATURES 18 MSPS Correlated Double Sampler (CDS) 6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Preblanking Function 10-Bit 18 MSPS A/D Converter 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power CMOS 48-Lead LQFP Package APPLICATIONS PC Cameras Digital Still Cameras PRODUCT DESCRIPTION The AD9804 is a complete analog signal processor for CCD applications. It features an 18 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9804’s signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled VGA, black level clamp, and a 10-bit A/D converter. The internal VGA gain register is programmed through a 3-wire serial digital interface. Complete 10-Bit 18 MSPS CCD Signal Processor AD9804 FUNCTIONAL BLOCK DIAGRAM PBLK AVDD AVSS CLPOB CCDIN CDS 6dB TO 40dB VGA CLP 10-BIT ADC DRVDD DRVSS 10 DOUT CLPDM CLP 10 VGA GAIN REGISTER AD9804 DIGITAL INTERFACE BANDGAP REFERENCE INTERNAL BIAS INTERNAL TIMING VR VTRB CML DVDD DVSS SL SCK SDATA SHP SHD DATACLK www.DataSheet4U.com REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page TIMING DIAGRAMS AD9804 CCD SIGNAL tID N SHP tS1 tID N+1 tS2 N+2 tCP N+9 SHD DATACLK tINH tOD tH OUTPUT DATA N–10 N–9 N–8 N–1 NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. Figure 1. Pixel Rate Timing N+10 N CCD SIGNAL EFFECTIVE PIXELS OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS CLPOB CLPDM www.DataSheet4U.com PBLK OUTPUT DATA EFFECTIVE PIXEL DATA OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA NOTES: 1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES. Figure 2. Typical Line Clamp Timing REV. 0 –5– 5 Page

Páginas	Total 8 Páginas
PDF Descargar	[ Datasheet AD9804.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AD9801	CCD Signal Processor For Electronic Cameras	Analog Devices
AD9802	CCD Signal Processor For Electronic Cameras	Analog Devices
AD9803	CCD Signal Processor	Analog Devices
AD9804	Complete 10-Bit 18 MSPS CCD Signal Processor	Analog Devices

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar