PDF AD9802 Data sheet ( Hoja de datos )

Número de pieza	AD9802
Descripción	CCD Signal Processor For Electronic Cameras
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES 10-Bit, 18 MSPS A/D Converter 18 MSPS Full Speed Correlated Double Sampler (CDS) Low Noise, Wideband PGA Internal Voltage Reference No Missing Codes Guaranteed +3 V Single Supply Operation Low Power CMOS: 185 mW 48-Terminal TQFP Package CCD Signal Processor For Electronic Cameras AD9802 FUNCTIONAL BLOCK DIAGRAM PBLK CLPDM PGACONT1 PGACONT2 SHP SHD ADCCLK PIN DIN ADCIN CLAMP TIMING GENERATOR CDS PGA MUX S/H 10 A/D DOUT REFERENCE CLAMP AD9802 DRVDD DVDD CMLEVEL VRT VRB STBY CLPOB ADCMODE ACVDD ADVDD PRODUCT DESCRIPTION The AD9802 is a complete CCD signal processor developed for electronic cameras. It is suitable for both camcorder and consumer-level still camera applications. The signal processing chain is comprised of a high speed CDS, variable gain PGA and 10-bit ADC. Required clamping cir- cuitry and an onboard voltage reference are provided as well as a direct ADC input. The AD9802 operates from a single +3 V supply with a typical power consumption of 185 mW. The AD9802 is packaged in a space saving 48-terminal thin quad flatpack (TQFP) and is specified over an operating tem- perature range of 0°C to +70°C. PRODUCT HIGHLIGHTS 1. On-Chip Input Clamp and CDS Clamp circuitry and high speed correlated double sampler allow for simple ac-coupling to interface a CCD sensor at full 18 MSPS conversion rate. 2. On-Chip PGA The AD9802 includes a low-noise, wideband amplifier with analog variable gain from 0 dB to 31.5 dB (linear in dB). 3. Direct ADC Input A direct input to the 10-bit A/D converter is provided for digitizing video signals. 4. 10-Bit, High Speed A/D Converter A linear 10-bit ADC is capable of digitizing CCD signals at the full 18 MSPS conversion rate. Typical DNL is ± 0.5 LSB and no missing code performance is guaranteed. 5. Low Power At 185 mW, and 15 mW in power-down, the AD9802 con- sumes a fraction of the power of presently available multichip solutions. 6. Digital I/O Functionality The AD9802 offers three-state digital output control. 7. Small Package Packaged in a 48-terminal, surface-mount thin quad flatpack, the AD9802 is well suited to very compact, low headroom designs. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997 1 page EQUIVALENT INPUT CIRCUITS DVDD DRVDD DVSS DRVSS Figure 1. Pins 2–11 (DB0–DB9) DVDD 200⍀ DSUBST DVSS Figure 2. Pin 21 (SHP) and Pin 22 (SHD) DVDD 200⍀ DSUBST DVSS Figure 3. Pin 16 (ADCCLK) ADVDD 9.3k⍀ ADVSS Figure 4. Pin 37 (CMLEVEL) ACVDD 50⍀ SUBST ACVSS Figure 5. Pin 25 (CCDBYP2) and Pin 28 (CCDBYP1) AD9802 ACVDD 50⍀ 10pF SUBST ACVSS Figure 6. Pin 26 (DIN) and Pin 27 (PIN) ACVDD PGACONT1 PGACONT2 SUBST ACVDD 8k⍀ 10k⍀ 1k⍀ 8k⍀ Figure 7. Pin 29 (PGACONT1) and Pin 30 (PGACONT2) ACVDD 200⍀ SUBST 10k⍀ 30k⍀ ACVSS Figure 8. Pin 32 (CLAMP BIAS) 3k⍀ ADVDD 1.1k⍀ 200⍀ SUBST ADVSS Figure 9. Pin 48 (VRT) and Pin 47 (VRB) ACVDD 50⍀ SUBST 1pF Figure 10. Pin 36 (ADCIN) and Pin 38 (SHABYP) REV. 0 –5– 5 Page droop specifications needed. A capacitor value of 0.01 µF will result in a droop of less than 10 LSB across one video line, and requires only a CLAMP pulse of 1 µs to charge up. A larger capacitor may be used to reduce droop, but then a longer CLAMP pulse may be necessary. 0 AD9802 1V p-p CIN CLAMP 500⍀ SD210 AD8047 500⍀ +3V ADCIN CML SHABYP SHA VRT VRB AD9802 ADCMODE Figure 26. Video Clamp Circuit 1.0 0.5 0 ؊0.5 ؊1.0 0 100 200 300 400 500 600 700 800 900 1023 Figure 27. Direct ADC-Mode Typical INL 1.0 0.5 0 ؊0.5 ؊1.0 0 100 200 300 400 500 600 700 800 900 1023 Figure 28. Direct ADC-Mode Typical DNL –100 0 FREQUENCY – MHz 9.0 Figure 29. Direct ADC Mode Typical FFT; FIN = 3.58 MHz, FS = 18 MHz Figures 27–29 show the typical linearity and distortion perfor- mance of the AD9802 in direct ADC mode. Digitally Programmable Gain Control The AD9802’s PGA is controlled by an analog input voltage of 0.3 V to 2.7 V. In some applications, digital gain control is preferable. Figure 30 shows a circuit using Analog Devices’ AD8402 Digital Potentiometer to generate the PGA control voltage. The AD8402 functions as two individual potentiom- eters, with a serial digital interface to program the position of each wiper over 256 positions. The device will operate with 3 V or 5 V supplies, and features a power-down mode and a reset function. To keep external components to a minimum, the ends of the “potentiometers” can be tied to ground and +3 V. One pot is used for the coarse gain adjust, PGACONT1, with steps of about 0.2 dB/LSB. The other pot is used for fine gain control, PGACONT2, and is capable of around 0.01 dB steps if all eight bits are used. The two outputs should be filtered with 1 µF or larger capacitors to minimize noise into the PGACONT pins of the AD9802. +3V PGACONT2 1␮F 1 14 2 13 3 12 AD8402-10 4 11 5 10 69 78 +3V 0.1␮F PGACONT1 +3V 1␮F SHDN CS SDI CLK RS Figure 30. Digital Control of PGA REV. 0 –11– 11 Page

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