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PDF SI8442 Data sheet ( Hoja de datos )
| Número de pieza | SI8442 | |
| Descripción | (SI8440 - SI8442) QUAD-CHANNEL DIGITAL ISOLATOR | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si8440/1/2
QUAD-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation:
DC – 150 Mbps
Low propagation delay:
<10 ns
Wide Operating Supply Voltage:
2.375–5.5 V
Low power: I1 + I2 <
12 mA/channel at 100 Mbps
Precise timing:
2 ns pulse width distortion
1 ns channel-channel matching
2 ns pulse width skew
2500 VRMS isolation
Transient Immunity: >25 kV/µs
Tri-state outputs with ENABLE
control
DC correct
No start-up initialization required
<10 µs Startup Time
High temperature operation:
125 °C at 100 Mbps
100 °C at 150 Mbps
Wide body SOIC-16 package
Applications
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power factor correction systems
Safety Regulatory Approvals
UL recognition:2500 VRMS for 1
Minute per UL1577
CSA component acceptance
notice #5A
* All Pending
VDE certification conformity
DIN EN 60747-5-2 (VDE0884
Part 2):2003-01
DIN EN60950(VDE0805):
2001-12;EN60950:2000
VIORM = 560 VPEAK
Description
Silicon Lab's family of digital isolators are CMOS devices that employ
www.DaatnaShReFet4cUo.cuopmler to transmit digital information across an isolation
barrier. Very high speed operation at low power levels is achieved.
These parts are available in a 16-pin wide body SOIC package. Three
speed grade options (1, 10, 100 Mbps) are available and achieve
typical propagation delay of less than 10 ns.
Block Diagram
Si8440
Si8441
Si8442
Pin Assignments
Wide Body SOIC
VDD1
GND1
A1
A2
A3
A4
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
VDD2
GND2
B1
B2
B3
B4
EN2
GND2
A1 B1 A1 B1 A1 B1
A2 B2 A2 B2 A2 B2
A3 B3 A3 B3 A3 B3
A4 B4 A4 B4 A4 B4
NC
EN2
EN1
EN2
EN1
EN2
Rev. 0.3 4/06
Copyright © 2006 by Silicon Laboratories
Si8440/1/2
1 page  
Si8440/1/2
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 C°)
Parameter
Symbol Test Condition
Min
Typ Max Unit
Timing Characteristics
Maximum Data Rate
0 — 100 Mbps
Minimum Pulse Width
Propagation Delay1
Pulse Width Distortion
|tPLH - tPHL|1
Propagation Delay Skew2
Channel-Channel Skew3
Output Rise Time
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
C1 = 15 pF
— 5 — ns
— 7.5 — ns
— 1 — ns
— 6 — ns
— 0.5 — ns
— 2 — ns
Output Fall Time
C1 = 15 pF — 2 — ns
Common Mode Transient
Immunity at Logic Low Output4
CML
25 30 — kV/µs
Common Mode Transient
Immunity at Logic High Output4
CMH
25 30 — kV/µs
Enable to Data Valid
ten1
— 5 — ns
Enable to Data Tri-State
Start-up Time5
ten2
tSU
— 5 — ns
— 3 — µs
Notes:
1. tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the
50% level of the rising edge of the VOx signal.
2. tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any
two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is
the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of
the isolation barrier.
www.DataSh4e. etC4UM.cHoims the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is
the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range
over which the common mode is slewed.
5. Start-up time is the time period from the application of power to valid data at the output.
ENABLE
OUTPUTS
ten1 ten2
Figure 1. ENABLE Timing Diagram
INPUT
(VIX)
50%
tPLH
tPHL
OUTPUT
(VOX)
50%
Figure 2. Propagation Delay Timing
Rev. 0.3
5
5 Page 
Si8440/1/2
Table 7. Regulatory Information
The Si84xx have been approved by the organizations listed below.
UL1
CSA
VDE2
Recognized under 1577 component
recognition program1
Basic insulation, 2500 V RMS
isolation voltage
File E257455
Approved under CSA Component
Acceptance Notice #5A
Reinforced insulation per CSA
60950-1-03 and IEC 60950-1, 400 V
RMS maximum working voltage
File 2500035643
Certified according to DIN EN
60747-5-2 (VDE 0884 Part 2): 2003-
012
Basic insulation, 560 V peak
Complies with DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-01, DIN EN
60950 (VDE 0805): 2001-12; EN
60950:2000 Reinforced insulation,
560 V peak
File 5006301-4880-0001
Notes:
1. In accordance with UL1577, each Si84xx is proof tested by applying an insulation test voltage > 3000 V RMS for 1
second (current leakage detection limit = 5 µA).
2. In accordance with DIN EN 60747-5-2, each Si84xx is proof tested by applying an insulation test voltage > 1050 V
peak for 1 second (partial discharge detection limit = 5 pC). A “*” mark branded on the component designates DIN EN
60747-5-2 approval.
Table 8. Insulation and Safety-related Specifications
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Minimum External Tracking (Creepage)
www.DaMtaiSnhimeeut4mU.cInomternal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking
Index)
Basic Isolation Group
Symbol
Test Condition
1 minute duration
L(IO1)
Measured from input terminals to out-
put terminals, shortest distance
through air
L(IO2)
Measured from input terminals to out-
put terminals, shortest distance path
along body
Insulation distance through insulation
CTI DIN IEC 112/VDE 0303 Part 1
Material Group
(DIN VDE 0110, 1/89, Table 1)
Value
2500
7.7 min
8.1
0.017
min
>175
IIIa
Unit
VRMS
mm
mm
mm
V
Rev. 0.3
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet SI8442.PDF ] | |
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