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PDF LTC4222 Data sheet ( Hoja de datos )
| Número de pieza | LTC4222 | |
| Descripción | Dual Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n Allows Safe Insertion Into a Live Backplane
n 10-Bit ADC Monitors Currents and Voltages
n I2C/SMBus Interface
n Wide Operating Voltage Range: 2.9V to 29V
n dI/dt Controlled Soft-Start
n High Side Drive for External N-Channel MOSFETs
n No External Gate Capacitors Required
n Input Overvoltage/Undervoltage Protection
n Optional Latchoff or Auto-Retry After Faults
n Alert Host After Faults
n Inrush Current Limit with Foldback
n Available in 32-Pin (5mm × 5mm) QFN and 36-Pin
SSOP Packages
APPLICATIONS
n Live Board Insertion
n Electronic Circuit Breakers
n Computers, Servers
n Platform Management
LTC4222
Dual Hot Swap Controller
with I2C Compatible
Monitoring
DESCRIPTION
The LTC®4222 Hot Swap™ controller allows two power
paths to be safely inserted and removed from a live back-
plane. Using external N-channel pass transistors, board
supply voltages and inrush currents are ramped up at an
adjustable rate. An I2C interface and onboard ADC allows
for monitoring of current, voltage and fault status for
each channel.
The device features adjustable, analog, foldback current
limit circuits and a Soft-Start circuit that sets the dI/dt of
the inrush currents. An I2C interface may configure the
part to latch off or automatically restart after the LTC4222
detects a fault on either channel.
The controller has additional features to interrupt the host
when a fault has occurred, notify when output power is
good, detect insertion of a load card and power-up either
automatically upon insertion or wait for an I2C command
to turn on.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 7330065.
TYPICAL APPLICATION
12V
0.1μF
34k
1.02k
3.4k
ON
SDA
SCL
ALERT
NC
0.1μF
3.3V
0.1μF
3.4k
1.02k
6.55k
Advanced Mezzanine Card Application
6mΩ Si7336ADP
10.2k
10Ω
UV1 VDD1
OV1
ON
SDA
SCL
ALERT
CONFIG
ADR0
ADR1
ADR2
INTVCC
GND
OV2
UV2 VDD2
SENSE1– GATE1 SOURCE1
FB1
GPIO1
EN1
ADIN1
TIMER
LTC4222
SS
ADIN2
EN2
GPIO2
FB2
SENSE2– GATE2 SOURCE2
10Ω 10nF
3.57k 10Ω
12PGOOD
1μF
68nF
AUXPGOOD
3.57k 10Ω
12V
7.4A
Start-Up Waveform with Sequencing
VIN1/2
10V/DIV
VOUT2
10V/DIV
CONTACT
BOUNCE
VOUT1
10V/DIV
GPIO
PGOOD
10V/DIV
50ms/DIV
4222 TA01b
300mΩ Si1046R
4.99k
4222 TA01a
BACKPLANE PLUG-IN
CARD
3.3V
150mA
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LTC4222
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
I2C Interface
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VADR(H)
ADR0, ADR1, ADR2 Input High Voltage
l INTVCC INTVCC INTVCC
– 0.8 – 0.4 – 0.2
V
IADR(IN,Z)
ADR0, ADR1, ADR2 Hi-Z Input Current
VADR(L)
ADR0, ADR1, ADR2 Input Low Voltage
IADR(IN)
VALERT(OL)
IALERT(OH)
ADR0, ADR1, ADR2 Input Current
ALERT Output Low Voltage
ALERT Input Current
VSDA,SCL(TH)
SDA, SCL Input Threshold
ISDA,SCL(OH)
SDA, SCL Input Current
VSDA(OL)
SDA Output Low Voltage
I2C Interface Timing
ADR0, ADR1, ADR2 = 0.8V,
INTVCC – 0.8V
ADR0, ADR1, ADR2 = 0V, INTVCC
IALERT = 3mA
ALERT = INTVCC
SCL, SDA = INTVCC
ISDA = 3mA
l5
0 –5
l 0.2 0.4 0.8
l –80
80
l 0.2 0.4
l ±1
l 1.5 1.7 1.9
l ±1
l 0.2 0.4
μA
V
μA
V
μA
V
μA
V
fSCL(MAX)
tBUF(MIN)
tHD,STA(MIN)
tSU,STA(MIN)
tSU,STO(MIN)
tHD,DAT(MIN)
tHD,DATO
tSU,DAT(MIN)
tSP
tRST
CX
SCL Clock Frequency
Bus Free Time Between Stop/Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time (Input)
Data Hold Time (Output)
Data Set-Up Time
Suppressed Spike Pulse Width
Stuck-Bus Reset Time
SCL, SDA Input Capacitance
Operates with fSCL ≤ fSCL(MAX)
SCL or SDA Held Low
SDAI Tied to SDAO (Note 5)
400 1000
0.12 1.3
100 600
30 600
140 600
30 100
300 600 900
30 600
50 110 250
25 32 40
10
kHz
μs
ns
ns
ns
ns
ns
ns
ns
ms
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 5V above
SOURCE. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: Integral Nonlinearity is defined as the deviation of a code from a
precise analog input voltage. Maximum specifications are limited by the
LSB step size and the single shot measurement. Typical specifications are
measured from 1/4, 1/2, 3/4 areas of the quantization band.
Note 5: Guaranteed by design and not subject to test.
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FUNCTIONAL DIAGRAM
LTC4222
FB
UV
0.4V
OV
INTVCC
10MA
1.235V
EN
VDD
1.235V +
UV
–
+
RST
–
RESET
+
OV1
1.235V –
+
EN
EN
–
2.43V +
UVLO1
–
0.2V FOLDBACK
0.6V and DIDT
UVS
SENSE–
SENSE+ (SSOP)
–
0mV TO
CB 50mV 150mV
CS
+– +
CHARGE
PUMP
AND
GATE
DRIVER
GATE
SOURCE
FAULT
+
PWRGD
OVS PG
1.235V –
FET ON
+
GP
– 1V
GPIO
VDD UVLO
LOGIC
+ ON
ONS
ON
– 1.235V
2x
1x
SS
CONFIG
+
1.235V –
SDAI (SSOP)
SDAO (SSOP)
SDA (QFN)
SCL
ALERT
I2C
SOFT-START
COUPLE
I2C ADDR 5
0.2V +
TM1
–
1.235V
+
TM2
–
INTVCC
100MA
VDD2
3.3V
GEN
2MA
VCC UVLO
+
UVLO2
–
2.64V
TIMER
INTVCC
ADIN1
ADIN2
SOURCE1
VDDA – SENSE1
SOURCE2
VDDB – SENSE2
A/D CONVERTER
10 BIT
1 OF 27
ADR0
ADR1
ADR2
4222 BD
4222f
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC4222.PDF ] | |
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