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PDF LTC4221 Data sheet ( Hoja de datos )
| Número de pieza | LTC4221 | |
| Descripción | Dual Hot Swap Controller/ Power Sequencer | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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www.DataSheet4U.com
LTC4221
Dual Hot Swap Controller/
Power Sequencer with Dual Speed,
Dual Level Fault Protection
FEATURES
■ Allows Safe Board Insertion and Removal from a
Live Backplane
■ Configurable Power Supply Sequencing
■ Soft-Start with Current Foldback Limits Inrush
Current
■ No External Gate Capacitor Required
■ Adjustable Dual Level Circuit Breaker Protection
■ Controls Supply Voltages from 1V to 13.5V
■ Independent N-Channel MOSFET High Side Drivers
■ FB Pin Monitors VOUT for Overvoltage Protection
■ Latch Off or Automatic Retry on Current Fault
■ FAULT and PWRGD Outputs
■ Narrow 16-Pin SSOP Package
U
APPLICATIO S
■ Electronic Circuit Breaker
■ Power Supply Sequencing
■ Live Board Insertion and Removal
■ Industrial High Side Switch/Circuit Breaker
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
DESCRIPTIO
The LTC®4221 is a 2-channel Hot SwapTM controller that
allows a board to be safely inserted and removed from a
live backplane. Using two independent high side gate
drivers to control two external N-channel pass transistors,
the output voltages can be ramped up with current foldback
to limit the inrush current during the start-up period. No
external compensation capacitors are required at the
GATE pins. The two channels can be configured to ramp up
and down separately or simultaneously for supply volt-
ages ranging from 2.7V to 13.5V and 1V to 13.5V for
channels 1 and 2 respectively.
Each channel has two current limit comparators that
provide dual level and dual speed overcurrent circuit
breaker protection after the start-up period. If any current
sense voltage exceeds 100mV for 1µs or 25mV for the
timeout delay (set by the CFILTER at the FILTER pin), then
the FAULT latch is set and both GATE pins are pulled low.
The FB pins monitor the respective channel output volt-
ages and provide the inputs for the PWRGD comparators
as well as overvoltage protection.
TYPICAL APPLICATIO
2-Channel Hot Swap Controller
VCC1
3.3V
VCC2
2.5V
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(FEMALE) (MALE)
LONG
LONG
*
SHORT
10Ω
100nF
21k
0.004Ω IRF7413
0.004Ω IRF7413
*
100nF
10k
10Ω
VCC1
ON1
SENSE1 GATE1 VCC2
SENSE2 GATE2 14.3k
FB2
5.11k
FAULT
GND
SHORT
13.3k
SHORT
LONG
*SMAJ10 (OPTIONAL)
10k
ON2
FAULT
GND
TIMER
LTC4221
470nF
PWRGD2
PWRGD1
FILTER FB1
1nF
VOUT1
3.3V/5A
VOUT2
2.5V/5A
10k 10k
PWRGD2
PWRGD1
20k
5.11k
4221 TA01
4221f
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC4221
VSENSE(ACL) vs VFB
30
VCC1 = 5V
VCC2 = 3.3V
25 TA = 25°C
20
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VFB (V)
4221 G10
IGATE(UP) vs Temperature
–6
VCC2 = 1V
VGATE = 0V
–7
–8
–9
–10
–11
–12
–50
VCC1 = 2.7V
VCC1 = 5V
VCC1 = 13.5V
–25 0 25 50 75
TEMPERATURE (°C)
100 125
4221 G11
IGATE(FSTDN) vs Temperature
60
VCC2 = 1V
VGATE = 3.3V
50
VCC1 = 2.7V
VCC1 = 5V
VCC1 = 13.5V
40
30
20
10
0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
4221 G13
∆VGATE2 (VGATE2 – VCC1)
vs Temperature
16
VCC1 = 2.7V, VCC2 = 1V
VCC1 = 5V, VCC2 = 3.3V
14 VCC1 = 13.5V, VCC2 = 13.5V
12
10
8
6
4
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
4221 G16
∆VGATEn (VGATEn – VCC1) vs VCC1
15
VCC2 = VCC1 – 1.5V
14 TA = 25°C
13 ∆VGATE1
12 ∆VGATE2
11
10
9
8
7
6
0 2 4 6 8 10 12 14
VCC1 (V)
4221 G14
VGATE(OV) vs Temperature
0.420
VCC2 = 1V
0.415 TIMER = 0.5V
0.410
VCC1 = 2.7V
VCC1 = 5V
VCC1 = 13.5V
0.405
0.400
0.395
0.390
0.385
0.380
0.375
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
4221 G17
IGATE(DN) vs Temperature
104
VCC2 = 1V
103 VGATE = 3.3V
102
101
100
99
98
97
–50 –25
VCC1 = 2.7V
VCC1 = 5V
VCC1 = 13.5V
0 25 50 75 100 125
TEMPERATURE (°C)
4221 G12
∆VGATE1 (VGATE1 – VCC1)
vs Temperature
18
VCC1 = 2.7V, VCC2 = 1V
16
VCC1 = 5V, VCC2 = 3.3V
VCC1 = 13.5V, VCC2 = 13.5V
14
12
10
8
6
4
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
4221 G15
VON(RESET) vs VCC1
0.430
VCC2 = 1V, TA = 25°C
0.425
RISING
0.420
0.415
0.410
0.405
0.400
FALLING
0.395
0 2 4 6 8 10 12 14 16
VCC1 (V)
4221 G18
4221f
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OPERATIO
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current may damage the connector pins and glitch the
power bus, causing other boards in the system to reset.
The LTC4221 is designed to turn on and off a circuit
board’s supply voltages in a controlled manner, allowing
insertion or removal without glitches or connector dam-
age. The LTC4221 can reside on the backplane or on the
removable circuit board for hot insertion applications. It
controls the path between the backplane power bus and
the daughter board load with an external MOSFET switch.
Both inrush control and short-circuit protection are pro-
vided by the external MOSFET. Each LTC4221 controls
two channels, each with its individual MOSFET for sup-
plies from 1V to 13.5V.
Overview
The timing diagram in Figure 1 shows some typical wave-
forms of the LTC4221. The VCC and GND pins receive
power through the longest connector pins and are the first
to connect when the board is inserted. During the under-
voltage lockout (UVLO) state before time point 1, both
GATE pins are held low by internal N-channel MOSFET
pull-downs, turning the external MOSFETs off. Once both
VCC pins are valid at time point 1, the LTC4221 enters into
a reset state as ON1 is below its reset threshold. At time
point 2, ON1 clears its reset threshold and the device goes
from the reset state to an off state. When either ON1 or
ON2 clears its off threshold, both GATE pins are < 0.4V and
TIMER < 0.4V (time points 3 and 4), the TIMER pin sources
1.9µA and an initial timing cycle starts. Any transition of
ON1 and ON2 through their off thresholds will reset the
initial timing cycle. At time point 5, TIMER reaches its high
threshold and is pulled down by an internal N-channel
MOSFET to its low threshold at time point 6. The LTC4221
then checks that FILTER pin voltage is low and FAULT pin
voltage is high. If both conditions are met, the electronic
circuit breaker is armed. The channel 1 start-up timing
cycle starts at time point 6 since ON1 has cleared its off
threshold and ON2 has not.
LTC4221
During the start-up cycle, TIMER sources 20µA and GATE1
sources 9.5µA. As GATE1 ramps up, MOSFET1 starts to
turn on and current flows through to charge up the load
capacitance. As VOUT1 and FB1 ramp up, the load current
is monitored through the external SENSE1 resistor. Be-
tween time points 7 and 8, the GATE1 9.5µA pull-up is
controlled to servo the voltage across RSENSE1 to be less
than the SENSE1 active current limit voltage, which has a
component controlled by the FB1 voltage (see Applica-
tions Information: Start-Up Cycle with Current Limit). In
this way, inrush current is limited and MOSFET1 does not
overheat during the start-up cycle. When FB1 clears its
undervoltage threshold, PWRGD1 asserts high. At time
point 9, TIMER reaches its high threshold and is pulled
down by an internal N-channel MOSFET to its low thresh-
old at time point 10. Channel 1’s slow comparator is armed
at time point 9 and enters a fault monitor mode, bringing
the channel 1 start-up cycle to an end.
At time point 10, ON2 voltage is monitored and since ON2
has cleared its off threshold, the start-up timing cycle
repeats for channel 2. The inrush current is low and GATE2
ramps up without need for current limiting. Channel 2’s
slow comparator is armed at time point 11 and enters a
fault monitor mode, ending the channel 2 start-up cycle.
Overcurrent faults translate to an increase in either VRSENSE.
At time point 13, VRSENSE1 > 25mV (slow comparator
threshold). The 1.8µA pull-down on the FILTER changes to
a 105µA pull-up. When the FILTER pin hits its threshold at
time point 14, it triggers a fault state when FAULT is
latched low and both GATE pins are pulled low by internal
N-channel MOSFETs, turning off the external MOSFETs.
As each channel output discharges, its FB pin goes below
the undervoltage threshold and the PWRGD pin deasserts.
Higher overcurrents when either VRSENSE > 100mV (fast
comparator threshold) for more than 1µs will trigger the
same condition. This fault state can only be cleared by a
UVLO at either VCC pin or a hard reset at the ON1 pin, as
at time point 15, when ON1 is pulled below its reset
threshold. The LTC4221 then reverts back to its reset state
as between time points 1 and 2.
4221f
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC4221.PDF ] | |
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