|
|
PDF CY23S05 Data sheet ( Hoja de datos )
| Número de pieza | CY23S05 | |
| Descripción | (CY23S05 / CY23S09) Zero Delay Buffer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY23S05 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
05
www.DataSheet4U.com
CY23S09
CY23S05
Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
Features
• 10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
• Zero input-output propagation delay
• Multiple low-skew outputs
— Output-output skew less than 250 ps
— Device-device skew less than 700 ps
— One input drives five outputs (CY23S05)
— One input drives nine outputs, grouped as 4 + 4 + 1
(CY23S09)
• Less than 200 ps cycle-to-cycle jitter is compatible with
Pentium-based systems
• Test Mode to bypass PLL (CY23S09 only, see Select
Input Decoding table on page 2)
• Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
• 3.3V operation, advanced 0.65µ CMOS technology
• Spread Aware™
Functional Description
The CY23S09 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an eight-pin version of the
CY23S09. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
Block Diagram
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The CY23S09 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the Select Input
Decoding table on page 2. If all output clocks are not required,
Bank B can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY23S09 and CY23S05 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 µA of current draw (for commercial temper-
ature devices) and 25.0 µA (for industrial temperature
devices). The CY23S09 PLL shuts down in one additional
case, as shown in the table below.
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-to-cycle jitter. The
input to output propagation delay on both devices is
guaranteed to be less than 350 ps, and the output to output
skew is guaranteed to be less than 250 ps.
The CY23S05/CY23S09 is available in two different configu-
rations, as shown in the ordering information on page 6. The
CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/
CY23S09-1H is the high-drive version of the -1, and its rise
and fall times are much faster than -1.
Pin Configuration
REF
S2
S1
PLL
MUX
Select Input
Decoding
CY23S09
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
SOIC/TSSOP/SSOP
Top View
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16 CLKOUT
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
CY23S09
REF
PLL
CY23S05
CLKOUT
CLK1
CLK2
CLK3
CLK4
SOIC
Top View
REF
CLK2
CLK1
GND
1
2
3
4
8 CLKOUT
7 CLK4
6 VDD
5 CLK3
CY23S05
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07296 Rev. *B
Revised December 22, 2002
1 page  
www.DataSheet4U.com
CY23S05
CY23S09
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices[8]
Parameter
Description
Test Conditions
Min.
Typ.
t1 Output Frequency
30-pF load
10-pF load
10
10
Duty Cycle[7] = t2 ÷ t1
Duty Cycle[7] = t2 ÷ t1
t3 Rise Time[7]
Measured at 1.4V, Fout = 66.67 MHz
Measured at 1.4V, Fout <50.0 MHz
Measured between 0.8V and 2.0V
40.0
45.0
50.0
50.0
t4 Fall Time[7]
Measured between 0.8V and 2.0V
t5 Output-to-Output Skew[7]
All outputs equally loaded
t6
Delay, REF Rising Edge to
CLKOUT Rising Edge[7]
Measured at VDD/2
0
t7
Device-to-Device Skew[7]
Measured at VDD/2 on the CLKOUT
pins of devices
0
t8
tJ
tLOCK
Output Slew Rate[7]
Cycle-to-Cycle Jitter[7]
PLL Lock Time[7]
Measured between 0.8V and 2.0V using
Test Circuit #2
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock
presented on REF pin
1
Max.
100
133.33
60.0
55.0
1.50
1.50
250
±350
700
200
1.0
Unit
MHz
MHz
%
%
ns
ns
ps
ps
ps
V/ns
ps
ms
Switching Waveforms
Duty Cycle Timing
1.4V
t1
t2
1.4V
1.4V
2309–4
All Outputs Rise/Fall Time
2.0V
OUTPUT 0.8V
t3
2.0V
0.8V
t4
3.3V
0V
2309–5
Output-Output Skew
OUTPUT
1.4V
OUTPUT
t5
1.4V
2309–6
Document #: 38-07296 Rev. *B
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY23S05.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY23S02 | Frequency Multiplier and Zero Delay Buffer | Cypress Semiconductor |
| CY23S05 | (CY23S05 / CY23S09) Zero Delay Buffer | Cypress Semiconductor |
| CY23S08 | 3.3V Zero Delay Buffer | Cypress Semiconductor |
| CY23S09 | (CY23S05 / CY23S09) Zero Delay Buffer | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |