PDF CY23S02 Data sheet ( Hoja de datos )

Número de pieza	CY23S02
Descripción	Frequency Multiplier and Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CY23S02 Spread Aware™, Frequency Multiplier and Zero Delay Buffer Features • Spread Aware™—designed to work with SSFTG reference signals • 90ps typical jitter OUT2 • 200ps typical jitter OUT1 • 65ps typical output-to-output skew • 90ps typical propagation delay • Voltage range: 3.3V±5%, or 5V±10% • Output frequency range: 20MHz-133MHz • Two outputs • Configuration options allow various multiplication of the reference frequency, refer to Table 1 to determine the specific option which meets your multiplication needs • Available in 8-pin SOIC package Table 1. Configuration Options FBIN FS0 FS1 OUT1 OUT1 0 0 2 X REF OUT1 1 0 4 X REF OUT1 0 1 REF OUT1 1 1 8 X REF OUT2 0 0 4 X REF OUT2 1 0 8 X REF OUT2 0 1 2 X REF OUT2 1 1 16 X REF OUT2 REF 2 X REF REF/2 4 X REF 2 X REF 4 X REF REF 8 X REF Block Diagram Pin Configuration FBIN FS0 FS1 ÷Q External feedback connection to OUT1 or OUT2, not both FBIN IN GND FS0 1 2 3 4 8 OUT2 7 VDD 6 OUT1 5 FS1 IN Reference Input Phase Detector Charge Pump Loop Filter Output Buffer VCO ÷2 Output Buffer OUT1 OUT2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07155 Rev. C Revised June 7, 2005 1 page www.DataSheet4U.com CY23S02 AC Electrical Characteristics: TA = 0°C to +70°C or –40° to 85°C, VDD = 3.3V±5% Parameter Description Test Condition Min. fIN Input Frequency[1] OUT2 = REF 10 fOUT Output Frequency OUT1 20 tR Output Rise Time 0.8V to 2.0V, 15-pF load — tF tICLKR tICLKF tPD tDC Output Fall Time Input Clock Rise Time[2] Input Clock Fall Time[2] FBIN to IN (Reference Input) Skew[3, 4] Duty Cycle[5] 2.0V to 0.8V, 15-pF load Note 5 — — — — 40 tLOCK tJC PLL Lock Time Jitter, Cycle-to-Cycle[6] Power supply stable OUT1 — OUT2 — tSKEW tPD Output-output Skew Propagation Delay — –350 Typ. — — — — — — — 50 — 200 90 65 90 Max. 133 133 3.5 2.5 10 10 300 60 1.0 300 300 250 350 Unit MHz MHz ns ns ns ns ps % ms ps ps ps ps AC Electrical Characteristics: TA = 0°C to +70°C or –40° to 85°C, VDD = 5V±10% Parameter Description Test Condition Min. fIN Input Frequency[1] OUT2 = REF 10 fOUT Output Frequency OUT1 20 tR Output Rise Time 0.8V to 2.0V, 15-pF load — tF tICLKR tICLKF tPD tD Output Fall Time Input Clock Rise Time[2] Input Clock Fall Time[2] FBIN to IN (Reference Input) Skew[3, 4] Duty Cycle[7, 8] 2.0V to 0.8V, 15-pF load — — — — 40 tLOCK tJC PLL Lock Time Jitter, Cycle-to-Cycle[6] Power supply stable OUT1 — — OUT2 — Typ. — — — — — — — 50 — 200 90 Max. 133 133 3.5 2.5 10 10 300 60 1.0 300 300 Unit MHz MHz ns ns ns ns ps % ms ps ps tSKEW tPD Output-output Skew Propagation Delay — 65 250 ps –350 90 350 ps Ordering Information Ordering Code CY23S02SI-1 CY23S02SI-1T Lead-free CY23S02SXI-1 CY23S02SXI-1T Package Type 8-pin SOIC (150 mil) 8-pin SOIC (150 mil) - Tape and Reel 8-pin SOIC (150 mil) 8-pin SOIC (150 mil) - Tape and Reel Temperature Grade Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Notes: 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V. 6. Jitter is measured on 133-MHz signal at 1.4V, low frequency jitter = 350 ps. 7. Duty cycle is measured at 1.4V, 120 MHz. 8. Duty cycle at 133 MHz is 35/65 worst case. Document #: 38-07155 Rev. C Page Page 5 of 7 of 7 5 Page

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