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PDF STLS2F02 Data sheet ( Hoja de datos )
| Número de pieza | STLS2F02 | |
| Descripción | High performance 64-bit superscalar MIPS microprocessor | |
| Fabricantes | STMicroelectronics | |
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STLS2F02
Loongson 2F
high performance 64-bit superscalar MIPS® microprocessor
Preliminary Data
Features
■ 64-bit superscalar architecture
■ 900 MHz clock frequency
■ Single/double precision floating-point units
■ New streaming multimedia instruction set
support (SIMD)
■ 64 Kbyte instruction cache, 64 Kbyte data
cache, on-chip 512 Kbyte unified L2 cache
■ On chip DDR2-667 and PCI-X controller
■ 4 W @ 900 MHz power consumption:
– Best in class for power management
– Voltage/frequency scaling
– Standby mode support
– L2 cache disable/enable option
■ Leading edge 90 nm process technology
■ 27x27 heat spreader flip-chip BGA package
■ MIPS based (compatible with MIPSIII)
instruction set
Description
The STLS2F02 is a MIPS based 64-bit
superscalar microprocessor, able to issue four
instructions per clock cycle among six functional
units: two integer, two single/double-precision
floating-point, one 64-bit SIMD and one load/store
unit.
The micro architecture is organized with nine
stages of pipeline and support of dynamic branch
prediction.
HFCBGA452 (27x27x2.9mm)
The memory hierarchy is composed by the first
level of 64 Kbyte 4-way set associative caches for
instructions and data, the second level of
512 Kbyte unified 4-way set associative cache
and the memory management unit with table
lookside buffer.
The Loongson microprocessor family is the
outcome of a successful collaboration started in
2004 between STMicroelectronics and the
Institute of Computing Technology, part of the
Chinese Academy of Science. Loongson
microprocessors were co-developed by
STMicroelectronics and the Institute of
Computing Technology to address all the
applications requiring high level of performance
and low power dissipation.
Compared to the STLS2E02 processor, the
STLS2F02 has an enhanced architecture
providing higher performances, reduced power
consumption, integrated DDR2 memory controller
and PCI-X bus interface.
Table 1.
Device summary
Order code
STLS2F02
Package
HFCBGA452 (27x27x2.9 mm)
Packing
Tray
August 2008
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Interface signal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STLS2F02 uniprocessor system connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STLS2F02 multiprocessor system connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Local bus read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Local bus write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DDR2 SDRAM row/column address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DDR2 SDRAM read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DDR2 SDRAM write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Initialization process when in main bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reflow temperature to time curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Pin arrangement (left-hand side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Pin arrangement (middle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pin arrangement (right-hand side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
HFCBGA452 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Interface description
2.4
Local bus signals
The local bus provides a simple bus interface for system boot ROM and IO device. The
interface is designed for chip-connect simplicity.
The local bus signals are shown in Table 4.
Table 4. Local bus signals
Name
Input/output
LIO_AD[15:0]
LIO_A[7:0]
LIO_CSn
LIO_ROMCSn
LIO_WRn
LIO_RDn
LIO_ADLOCK
LIO_DIR
LIO_DEN
I/O
O
O
O
O
O
O
O
O
Description
Local IO address and data bus
(when ADLOCK valid output the most significant 16-bit)
Lowest significant 8-bit address bus
Local IO chip select
Local IO ROM chip select
Local IO write enable
Local IO read enable
Local IO address lock
Local IO direction
Local IO device enable
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STLS2F02.PDF ] | |
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