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PDF LTC2224 Data sheet ( Hoja de datos )
| Número de pieza | LTC2224 | |
| Descripción | 135Msps ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2224 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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LTC2224
12-Bit, 135Msps ADC
FEATURES
www.datasheet4u.com
■ Sample Rate: 135Msps
■ 67.3dB SNR up to 140MHz Input
■ 80dB SFDR up to 150MHz Input
■ 775MHz Full Power Bandwidth S/H
■ Single 3.3V Supply
■ Low Power Dissipation: 630mW
■ CMOS Outputs
■ Selectable Input Ranges: ±0.5V or ±1V
■ No Missing Codes
■ Optional Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
■ Data Ready Output Clock
■ Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
■ 48-Pin 7mm × 7mm QFN Package
U
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Cable Head-End Systems
■ Power Amplifier Linearization
■ Communications Test Equipment
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
VDD
ANALOG
INPUT
+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
DESCRIPTIO
The LTC®2224 is a 135Msps, sampling 12-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. The LTC2224 is perfect for demand-
ing communications applications with AC performance
that includes 67.3dB SNR and 80dB spurious free dy-
namic range for signals up to 150MHz. Ultralow jitter of
0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSBRMS.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
OUTPUT
DRIVERS
0.5V TO 3.6V
OVDD
D11
•
•
•
D0
OGND
2224 TA01
SFDR vs Input Frequency
95
90
4th OR HIGHER
85
80
75
2nd OR 3rd
70
65
60
55
50
0
100 200 300 400 500 600
INPUT FREQUENCY (MHz)
2224 TA01b
2224fa
1
1 page  
LTC2224
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
wwwV.dDaDtasheet4u.comAnalog Supply Voltage
OVDD
Output Supply Voltage
IVDD Analog Supply Current
● 3.1 3.3 3.5
● 0.5 3.3 3.6
● 191 206
V
V
mA
PDISS
Power Dissipation
●
630 680
mW
PSHDN
Shutdown Power
SHDN = High, OE = High, No CLK
2 mW
PNAP
Nap Mode Power
SHDN = High, OE = Low, No CLK
35 mW
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fS
tL
PARAMETER
Sampling Frequency
ENC Low Time
tH ENC High Time
tAP Sample-and-Hold Aperture Delay
tOE Output Enable Delay
tD ENC to DATA Delay
tC ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
Pipeline Latency
CONDITIONS
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
(Note 7)
(Note 7)
(tC - tD) (Note 7)
MIN TYP MAX
UNITS
●1
135 MHz
● 3.5 3.7 500
● 2 3.7 500
ns
ns
● 3.5 3.7 500
● 2 3.7 500
ns
ns
0 ns
●
5 10
ns
● 1.3 2.1 3.5
ns
● 1.3 2.1 3.5
ns
● –0.6 0 0.6
ns
5 Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they will
be clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential
ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive,
unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a “best
straight line” fit to the transfer curve. The deviation is measured from the
center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when the
output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential
ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive,
output CLOAD = 5pF.
2224fa
5
5 Page 
TI I G DIAGRA S
LTC2224
www.datasheet4u.com
ANALOG
INPUT
ENC–
ENC+
D0-D11, OF
CLOCKOUT
OE
DATA
Timing Diagram
tAP
N
tH N + 1
tL
N+2
N+3
N+4
tD
N–5
tC
N–4
N–3
N–2
N–1
2224 TD01
tOE tOE
OF, D0-D11, CLOCKOUT
2224fa
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2224.PDF ] | |
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