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PDF LTC2220-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC2220-1 | |
| Descripción | 185Msps ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2220-1
12-Bit,185Msps ADC
FEATURES
www.datasheet4u.com
■ Sample Rate: 185Msps
■ 67.5dB SNR up to 140MHz Input
■ 80dB SFDR up to 170MHz Input
■ 775MHz Full Power Bandwidth S/H
■ Single 3.3V Supply
■ Low Power Dissipation: 910mW
■ LVDS, CMOS, or Demultiplexed CMOS Outputs
■ Selectable Input Ranges: ±0.5V or ±1V
■ No Missing Codes
■ Optional Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
■ Data Ready Output Clock
■ Pin Compatible Family
185Msps: LTC2220-1 (12-Bit)
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
■ 64-Pin 9mm × 9mm QFN Package
U
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Cable Head-End Systems
■ Power Amplifier Linearization
■ Communications Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
DESCRIPTIO
The LTC®2220-1 is a 185Msps, sampling 12-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2220-1 is perfect for
demanding communications applications with AC perfor-
mance that includes 67.5dB SNR and 80dB spurious free
dynamic range for signals up to 170MHz. Ultralow jitter of
0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.7LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSBRMS.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
VDD
ANALOG
INPUT
+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
OUTPUT
DRIVERS
0.5V
TO 3.6V
OVDD
D11
• CMOS
• OR
• LVDS
D0
OGND
22201 TA01
SFDR vs Input Frequency
100
90
4th OR HIGHER
80
70
2nd OR 3rd
60
50
40
0 100 200 300 400 500 600
INPUT FREQUENCY (MHz)
22201 TA01b
2220_1fa
1
1 page  
LTC2220-1
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
wwwV.dDaDtasheet4u.com Analog Supply Voltage
PSHDN
Shutdown Power
PNAP Nap Mode Power
LVDS OUTPUT MODE
OVDD
Output Supply Voltage
IVDD Analog Supply Current
IOVDD
Output Supply Current
PDISS
Power Dissipation
CMOS OUTPUT MODE
OVDD
IVDD
PDISS
Output Supply Voltage
Analog Supply Current
Power Dissipation
CONDITIONS
(Note 8)
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
(Note 8)
(Note 8)
MIN TYP MAX UNITS
● 3.1 3.3 3.5
V
2 mW
35 mW
●3
●
●
●
3.3 3.6
273 300
55 70
1080 1221
V
mA
mA
mW
● 0.5 3.3 3.6
● 273 300
910
V
mA
mW
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fS Sampling Frequency
tL ENC Low Time (Note 7)
tH ENC High Time (Note 7)
tAP Sample-and-Hold Aperture Delay
tOE Output Enable Delay
LVDS OUTPUT MODE
(Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●1
● 2.5
●2
● 2.5
●2
●
185
2.7 500
2.7 500
2.7 500
2.7 500
0
5 10
MHz
ns
ns
ns
ns
ns
ns
tD ENC to DATA Delay
(Note 7)
tC
ENC to CLOCKOUT Delay
(Note 7)
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
Rise Time
● 1.3
● 1.3
● –0.6
2.2
2.2
0
0.5
3.5
3.5
0.6
ns
ns
ns
ns
Fall Time
0.5 ns
Pipeline Latency
5 ns
CMOS OUTPUT MODE
tD
tC
Pipeline Latency
ENC to DATA Delay
ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
Full Rate CMOS
(Note 7)
(Note 7)
(tC - tD) (Note 7)
● 1.3
● 1.3
● –0.6
2.1
2.1
0
5
3.5 ns
3.5 ns
0.6 ns
Cycles
Demuxed Interleaved
5 Cycles
Demuxed Simultaneous
5 and 6
Cycles
2220_1fa
5
5 Page 
W
FUNCTIONAL BLOCK DIAGRA
LTC2220-1
AIN+
www.datasheet4u.com
INPUT
AIN– S/H
VCM
2.2µF
1.6V
REFERENCE
RANGE
SELECT
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
VDD
GND
SHIFT REGISTER
AND CORRECTION
SENSE
REF
BUF
REFH
REFL INTERNAL CLOCK SIGNALS
DIFFERENTIAL
DIFF
REF
AMP
INPUT
LOW JITTER
CLOCK
CONTROL
LOGIC
DRIVER
REFLB REFHA
2.2µF
0.1µF
1µF
REFLA REFHB
0.1µF ENC+
1µF
ENC–
M0DE LVDS SHDN OE
Figure 1. Functional Block Diagram
OUTPUT
DRIVERS
OVDD
+
+–
–
OF
D11
•
•
•
+
–+
–
D0
CLKOUT
OGND
22201 F01
2220_1fa
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2220-1.PDF ] | |
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