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PDF LTC2222-11 Data sheet ( Hoja de datos )
| Número de pieza | LTC2222-11 | |
| Descripción | 105Msps ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2222-11
www.DataSheet4U.com
11-Bit, 105Msps ADC
FEATURES
■ Sample Rate: 105Msps
■ 65.4dB SNR up to 140MHz Input
■ 80dB SFDR up to 150MHz Input
■ 775MHz Full Power Bandwidth S/H
■ Single 3.3V Supply
■ Low Power Dissipation: 475mW
■ CMOS Outputs
■ Selectable Input Ranges: ±0.5V or ±1V
■ No Missing Codes
■ Optional Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
■ Data Ready Output Clock
■ Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
■ 48-Pin 7mm × 7mm QFN Package
U
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Cable Head-End Systems
■ Power Amplifier Linearization
■ Communications Test Equipment
DESCRIPTIO
The LTC®2222-11 is a 105Msps, sampling 11-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2222-11 is perfect for
demanding communications applications with AC perfor-
mance that includes 65.4dB SNR and 80dB spurious free
dynamic range for signals up to 150MHz. Ultralow jitter of
0.15psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.15LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.3V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
VDD
ANALOG
INPUT
+
INPUT
S/H
–
11-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
OUTPUT
DRIVERS
0.5V TO 3.3V
OVDD
D10
•
•
•
D0
OGND
222211 TA01
SFDR vs Input Frequency
95
90
4th OR HIGHER
85
80
75
2nd OR 3rd
70
65
60
55
50
0
100 200 300 400 500 600
INPUT FREQUENCY (MHz)
222211 TA01b
222211f
1
1 page  
LTC2222-11
www.DataSheet4U.com
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
VDD Analog Supply Voltage
● 3.1 3.3 3.5
V
OVDD
IVDD
Output Supply Voltage
Analog Supply Current
● 0.5 3.3 3.6
● 144 162
V
mA
PDISS
Power Dissipation
●
475 535
mW
PSHDN
Shutdown Power
SHDN = High, OE = High, No CLK
2 mW
PNAP
Nap Mode Power
SHDN = High, OE = Low, No CLK
35 mW
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fS
tL
PARAMETER
Sampling Frequency
ENC Low Time
tH ENC High Time
tAP Sample-and-Hold Aperture Delay
tOE Output Enable Delay
tD ENC to DATA Delay
tC ENC to CLOCKOUT Delay
DATA to CLOCKOUT Skew
Pipeline Latency
CONDITIONS
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
(Note 7)
(Note 7)
(tC - tD) (Note 7)
MIN TYP MAX
UNITS
●1
105 MHz
● 4.5 4.76 500
● 3 4.76 500
ns
ns
● 4.5 4.76 500
● 3 4.76 500
ns
ns
0 ns
●
5 10
ns
● 1.3 2.1 4
ns
● 1.3 2.1 4
ns
● –0.6 0 0.6
ns
5 Cycles
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 105MHz, differential
ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive,
unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
“best straight line” fit to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 000 0000 0000 and 111 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 105MHz, differential
ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive,
output CLOAD = 5pF.
222211f
5
5 Page 
TI I G DIAGRA S
LTC2222-11
www.DataSheet4U.com
Timing Diagram
ANALOG
INPUT
ENC–
ENC+
D0-D10, OF
CLOCKOUT
OE
DATA
tAP
N
tH N + 1
tL
N+2
N+3
N+4
tD
N–5
tC
N–4
N–3
N–2
N–1
222211 TD01
tOE tOE
OF, D0-D10, CLOCKOUT
222211f
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2222-11.PDF ] | |
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