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PDF CPC5621 Data sheet ( Hoja de datos )
| Número de pieza | CPC5621 | |
| Descripción | (CPC5620 / CPC5621) Phone Line Interface IC | |
| Fabricantes | Clare | |
| Logotipo |  |
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CPC5620/CPC5621
LITELINK™ III Phone Line Interface IC (DAA)
Features
• Superior voice solution with high power option, low
noise, no automatic gain control circuit, and excel-
lent part-to-part gain accuracy
• Data access arrangement (DAA) solution for modems at
speeds up to V.92
• 3.3 or 5 V power supply operation
• Caller ID signal reception function
• Easy interface with modem ICs and voice CODECs
• Worldwide dial-up telephone network compatibility
• Supplied application circuit complies with the
requirements of TIA/EIA/IS-968 (FCC part 68),
UL1950, UL60950, EN60950, IEC60950,
EN55022B, CISPR22B, EN55024, and TBR-21
• Complies with UL1577
• Line-side circuit powered from telephone line
• Compared to other silicon DAA solutions, LITELINK:
- Uses fewer passive components
- Takes up less printed-circuit board space
- Uses less telephone line power
- Offers simplified operation
- Is a single-chip solution
Applications
• Computer telephony and gateways, such as VoIP
• PBXs
• Satellite and cable set-top boxes
• V.92 (and other standard) modems
• Fax machines
• Voicemail systems
• Embedded modems for POS terminals, automated
banking, remote metering, vending machines, secu-
rity, and surveillance
Description
LITELINK III is a single-package silicon phone line
interface/DAA used in voice and data communication
applications to make connections between host equip-
ment and telephone networks.
LITELINK provides a high-voltage isolation barrier, AC
and DC phone line termination, switchhook, 2-wire to
4-wire hybrid, ring detection, and on-hook signal
detection. LITELINK can be used in both differential
and single-ended signal applications.
LITELINK uses on-chip optical components and a few
inexpensive external components to form a complete
voice or high-speed data phone line interface.
LITELINK eliminates the need for the large isolation
transformers or capacitors used in other interface con-
figurations. It incorporates the required high-voltage
isolation barrier in the surface-mount SOIC package.
The CPC5620 (half-wave ring detect) and CPC5621
(full-wave ring detect) PLIs build upon Clare’s
LITELINK II line, with improved insertion loss control,
improved noise performance, and lower minimum cur-
rent draw from the phone line.
Ordering Information
Part Number
CPC5620A
CPC5620ATR
CPC5621A
CPC5621ATR
Description
32-pin PLI with half-wave ring detect, tubed
32-pin PLI with half-wave ring detect, tape
and reel
32-pin PLI with full-wave ring detect, tubed
32-pin PLI with full-wave ring detect, tape and
reel
Figure 1. CPC5620/CPC5621 Block Diagram
Tx+
Tx-
MODE
OH
RING
CID
Rx+
Rx-
Transmit
Diff.
Amplifier
Isolation Barrier
Transmit
Isolation
Amplifier
Transconductance
Stage
2-4 Wire Hybrid
AC/DC Termination
Hookswitch
Receive
Diff.
Amplifier
Vref
Gain Trim
CID/
RING
MUX
Vref
Gain Trim
Receive
Isolation
Amplifier
Snoop Amplifier
CSNOOP
CSNOOP
RSNOOP
RSNOOP
TIP+
VI Slope Control
AC Impedance Control
Current Limit Control
RING-
DS-CPC5620/5621-R0.E
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1
1 page  
1.3 Pin Description
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Pin Name Function
1 VDD
2 TXSM
3 TX-
4 TX+
5 TX
6 MODE
7 GND
8 OH
9 RING
10 CID
11 RX-
12 RX+
13 SNP+
14 SNP-
15 RXF
16 RX
17 VDDL
18 RXS
19 RPB
20 BR-
21 ZDC
22 DCS2
23 DCS1
24 NTF
25 GAT
26 NTS
27 BR-
28 TXSL
29 ZNT
30 ZTX
31 TXF
32 REFL
Host (CPE) side power supply
Transmit summing junction
Negative differential transmit signal to DAA
from host
Positive differential transmit signal to DAA from
host
Transmit differential amplifier output
When asserted low, changes gain of TX path
(-7 dB) and RX path (+7 dB) to accommodate
reactive termination networks
Host (CPE) side analog ground
Assert logic low for off-hook operation
Indicates ring signal, pulsed high to low
Assert logic low while on hook to place CID
information on RX pins.
Negative differential analog signal received
from the telephone line. Must be AC coupled
with 0.1 µF.
Positive differential analog signal received from
the telephone line. Must be AC coupled with
0.1 µF.
Positive differential snoop input
Negative differential snoop input
Receive photodiode amplifier output
Receive photodiode summing junction
Power supply for line side, regulated from tip
and ring.
Receive isolation amp summing junction
Receive LED pre-bias current set
Bridge rectifier return
Electronic inductor DCR/current limit
DC feedback output
V to I slope control
Network amplifier feedback
External MOSFET gate control
Receive signal input
Bridge rectifier return
Transmit photodiode summing junction
Receiver impedance set
Transmit transconductance gain set
Transmit photodiode amplifier output
1.25 Vdc reference
Figure 2. Pinout
1 VDD
2 TXSM
3 TX-
4 TX+
5 TX
6 MODE
7 GND
8 OH
9 RING
10 CID
11 RX-
12 RX+
13 SNP+
14 SNP-
15 RXF
16 RX
CPC5620/CPC5621
REFL
TXF
ZTX
ZNT
TXSL
BR-
NTS
GAT
NTF
DCS1
DCS2
ZDC
BR-
RPB
RXS
VDDL
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Rev. 0.E
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5
5 Page 
typical operation. The ring detection threshold can be
cwhwawn.gDeadtaSahceceot4rdUi.ncgomto the following formula:
VRINGPK
=
7---5---R0----m3-----V--
(2R6 + R3)2 + (---π----f-R----I--N-1--G----C----7---)--2-
Clare Application Note AN-117 Customize Caller ID Gain
and Ring Detect Voltage Threshold is a spreadsheet for
trying different component values in this circuit.
Changing the ring detection threshold will also change
the caller ID gain and the timing of the polarity reversal
detection pulse, if used.
3.2.2 Polarity Reversal Detection with
CPC5621
The full-wave ring detector in the CPC5621 makes it
possible to detect tip and ring polarity reversal using
the RING output. When the polarity of tip and ring
reverses, a pulse on RING indicates the event. Your
host system must be able to discriminate this single
pulse of approximately 1 msec (using the recom-
mended snoop circuit external components) from a
valid ringing signal.
3.2.3 On-hook Caller ID Signal Reception
On-hook caller ID (CID) signals are processed by
LITELINK by coupling the CID data burst through the
snoop circuit to the LITELINK RX outputs under con-
trol of the CID pin. In North America, CID data signals
are typically sent between the first and second ringing
signal.
Figure 5. On-hook Caller ID Signal Timing in
North America for CPC5620 (with Half-
wave Ring Detect)
2s 500 ms
3s
475 ms 2s
RING First Ring
Caller ID data
Second Ring
CID
Signal levels not to scale
CPC5620/CPC5621
In North American applications, follow these steps to
receive on-hook caller ID data via the LITELINK RX
outputs:
1. Detect the first ringing signal outputs on RING.
2. Assert CID low.
3. Process the CID data from the RX outputs.
4. De-assert CID (high or floating).
Note: Taking LITELINK off-hook (via the OH pin) dis-
connects the snoop path from both the receive outputs
and the RING output, regardless of the state of the
CID pin.
CID gain from tip and ring to RX+ and RX- is deter-
mined by:
GAINCID(dB) = 20log ----------------------------6----R----3----------------------------
(2R6 + R3)2 + (---π----f--C1----7---)--2-
where ƒ is the frequency of the CID data signal.
The recommended components in the application cir-
cuit yield a gain 0.27 dB at 200 Hz. Clare Application
Note AN-117 Customize Caller ID Gain and Ring Detect
Voltage Threshold is a spreadsheet for trying different
component values in this circuit. Changing the CID
gain will also change the ring detection threshold and
the timing of the polarity reversal detection pulse, if
used.
For single-ended snoop circuit output of 0 dBm, set
the total resistance across the series resistors (R6/
R44 and R7/R45) to 1.4 MΩ.
3.3 Off-Hook Operation
3.3.1 Receive Signal Path
Signals to and from the telephone network appear on
the tip and ring connections of the application circuit.
Receive signals are extracted from transmit signals by
the LITELINK two-wire to four-wire hybrid. Next, the
receive signal is converted to infrared light by the
receive photodiode amplifier and receive path LED.
The intensity of the light is modulated by the receive
signal and coupled across the electrical isolation bar-
rier by a reflective dome.
On the host equipment side of the barrier, the receive
signal is converted by a photodiode into a photocur-
Rev. 0.E
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11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CPC5621.PDF ] | |
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