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Número de pieza | CMP0817BA0-I | |
Descripción | CMOS LPRAM | |
Fabricantes | Fidelix | |
Logotipo | ||
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Document Title
512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM
www.DataSheet4U.com
Revision History
Revision
No.
0.0
0.1
0.2
History
Initial Draft
Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions
Removed 60ns descriptions
CMOS LPRAM
Draft date
May. 2nd, 2004
Oct. 26th, 2005
Aug. 22nd, 2006
Remark
Final
Final
Final
1 Revision 0.2
Aug. 2006
1 page CMP0817BA0-I
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
wInwpuwt.pDualstaeSlehveeel :t40U.2.ctoomVCC-0.2V
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : CL=30pF+1TTL
CMOS LPRAM
30pf
1TTL
AC CHARACTERISTICS(VCC=2.7V~3.3V, Industrial product : TA=-40 to 85’C)
Parameter List
Symbol
70ns
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Min Max
tRC 70 80k
tAA -
70
tCO -
70
tOE -
25
/UB, /LB Access Time
tBA -
70
Read
Chip Select to Low-Z Output
/UB, /LB Enable to Low-Z Output
tLZ
tBLZ
10
10
-
-
Output Enable to Low-Z Output
tOLZ
5
-
Chip Disable to High- Z Output
tHZ 0
5
/UB, /LB Disable to High- Z Output
tBHZ
0
5
Output Disable to High- Z Output
tOHZ
0
5
Output Hold from Address Change
tOH 5
-
Write Cycle Time
tWC 70 80k
Chip Select to End of Write
tCW 60
-
Address Set-up Time
tAS 0
-
Address Valid to End of Write
tAW 60
-
Write
/UB, /LB Valid to End of Write
Write Pulse Width
tBW 60
tWP 50
-
-
Write Recovery Time
tWR 0
-
Write to Output High-Z
tWHZ
0
5
Data to Write Time Overlap
tDW 20
-
Data Hold from Write Time
End Write to Output Low-Z
/CS High Pulse Width1)
tDH
tOW
tCP
0
5
10
-
-
-
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 Revision 0.2
Aug. 2006
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet CMP0817BA0-I.PDF ] |
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