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PDF LM3S101 Data sheet ( Hoja de datos )

Número de pieza LM3S101
Descripción Microcontroller
Fabricantes Luminary　
Logotipo Luminary Logotipo



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No Preview Available ! LM3S101 Hoja de datos, Descripción, Manual

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PRELIMINARY
LM3S101 Microcontroller
DATA SHEET
DS-LM3S101-05
Copyright © 2006 Luminary Micro, Inc.

1 page




LM3S101 pdf
LM3S101 Data Sheet
10.5 Register Descriptions......................................................................................................................... 169
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.4
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Universal Asynchronous Receiver/Transmitter (UART)................................................ 190
Block Diagram ................................................................................................................................... 191
Functional Description ....................................................................................................................... 191
Transmit/Receive Logic ..................................................................................................................... 191
Baud-Rate Generation ....................................................................................................................... 192
Data Transmission ............................................................................................................................. 193
FIFO Operation .................................................................................................................................. 193
Interrupts............................................................................................................................................ 193
Loopback Operation .......................................................................................................................... 194
Initialization and Configuration........................................................................................................... 194
Register Map ..................................................................................................................................... 195
Register Descriptions......................................................................................................................... 196
12. Synchronous Serial Interface (SSI) ................................................................................. 226
12.1 Block Diagram ................................................................................................................................... 226
12.2 Functional Description ....................................................................................................................... 227
12.2.1 Bit Rate Generation ........................................................................................................................... 227
12.2.2 FIFO Operation .................................................................................................................................. 227
12.2.3 Interrupts............................................................................................................................................ 227
12.2.4 Frame Formats .................................................................................................................................. 228
12.3 Initialization and Configuration........................................................................................................... 235
12.4 Register Map ..................................................................................................................................... 236
12.5 Register Descriptions......................................................................................................................... 237
13. Analog Comparators......................................................................................................... 261
13.1 Block Diagram ................................................................................................................................... 261
13.2 Functional Description ....................................................................................................................... 261
13.2.1 Internal Reference Programming....................................................................................................... 263
13.3 Initialization and Configuration........................................................................................................... 264
13.4 Register Map ..................................................................................................................................... 265
13.5 Register Descriptions......................................................................................................................... 265
14. Pin Diagram ....................................................................................................................... 273
15. Signal Tables ..................................................................................................................... 274
16. Operating Characteristics ................................................................................................ 281
17. Electrical Characteristics ................................................................................................. 282
17.1 DC Characteristics ............................................................................................................................. 282
17.1.1 Maximum Ratings .............................................................................................................................. 282
17.1.2 Recommended DC Operating Conditions ......................................................................................... 282
17.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics .................................................................. 283
17.1.4 Power Specifications ......................................................................................................................... 284
17.1.5 Flash Memory Characteristics ........................................................................................................... 284
17.2 AC Characteristics ............................................................................................................................. 285
17.2.1 Load Conditions ................................................................................................................................. 285
17.2.2 Clocks ................................................................................................................................................ 285
17.2.3 Analog Comparator............................................................................................................................ 286
17.2.4 Synchronous Serial Interface (SSI) ................................................................................................... 287
17.2.5 JTAG and Boundary Scan ................................................................................................................. 289
17.2.6 General-Purpose I/O.......................................................................................................................... 291
17.2.7 Reset ................................................................................................................................................. 291
October 5, 2006
Preliminary
5

5 Page





LM3S101 arduino
LM3S101 Data Sheet
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
www.DataSheet4UR.ecogmister 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
GPIO Interrupt Event (GPIOIEV), offset 0x40C....................................................................... 109
GPIO Interrupt Mask (GPIOIM), offset 0x410.......................................................................... 110
GPIO Raw Interrupt Status (GPIORIS), offset 0x414.............................................................. 111
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ........................................................ 112
GPIO Interrupt Clear (GPIOICR), offset 0x41C....................................................................... 113
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ................................................. 114
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500.............................................................. 115
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504.............................................................. 116
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508.............................................................. 117
GPIO Open Drain Select (GPIOODR), offset 0x50C............................................................... 118
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ...................................................................... 119
GPIO Pull-Down Select (GPIOPDR), offset 0x514.................................................................. 120
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518...................................................... 121
GPIO Digital Input Enable (GPIODEN), offset 0x51C ............................................................. 122
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ........................................... 123
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ........................................... 124
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ........................................... 125
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC........................................... 126
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ........................................... 127
GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 ............................................ 128
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ........................................... 129
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC........................................... 130
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .............................................. 131
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .............................................. 132
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .............................................. 133
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC.............................................. 134
General-Purpose Timers .............................................................................................................. 135
Register 1: GPTM Configuration (GPTMCFG), offset 0x000..................................................................... 147
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 .................................................................. 148
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 .................................................................. 149
Register 4: GPTM Control (GPTMCTL), offset 0x00C............................................................................... 150
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .................................................................... 152
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .......................................................... 154
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ..................................................... 155
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024..................................................................... 156
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ...................................................... 157
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C...................................................... 158
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ....................................................... 159
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ....................................................... 160
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038.............................................................. 161
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ............................................................. 162
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040................................................ 163
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044................................................ 164
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................... 165
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C .............................................................................. 166
Watchdog Timer............................................................................................................................ 167
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ............................................................................ 170
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ......................................................................... 171
October 5, 2006
Preliminary
11

11 Page







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