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PDF LM3S102 Data sheet ( Hoja de datos )

Número de pieza LM3S102
Descripción Microcontroller
Fabricantes Luminary　
Logotipo Luminary Logotipo



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No Preview Available ! LM3S102 Hoja de datos, Descripción, Manual

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PRELIMINARY
LM3S102 Microcontroller
DATA SHEET
DS-LM3S102-04
Copyright © 2006 Luminary Micro, Inc.

1 page




LM3S102 pdf
LM3S102 Data Sheet
10.5 Register Descriptions......................................................................................................................... 172
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.4
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Universal Asynchronous Receiver/Transmitter (UART)................................................ 193
Block Diagram ................................................................................................................................... 194
Functional Description ....................................................................................................................... 194
Transmit/Receive Logic ..................................................................................................................... 194
Baud-Rate Generation ....................................................................................................................... 195
Data Transmission ............................................................................................................................. 196
FIFO Operation .................................................................................................................................. 196
Interrupts............................................................................................................................................ 196
Loopback Operation .......................................................................................................................... 197
Initialization and Configuration........................................................................................................... 197
Register Map ..................................................................................................................................... 198
Register Descriptions......................................................................................................................... 199
12. Synchronous Serial Interface (SSI) ................................................................................. 229
12.1 Block Diagram ................................................................................................................................... 229
12.2 Functional Description ....................................................................................................................... 230
12.2.1 Bit Rate Generation ........................................................................................................................... 230
12.2.2 FIFO Operation .................................................................................................................................. 230
12.2.3 Interrupts............................................................................................................................................ 230
12.2.4 Frame Formats .................................................................................................................................. 231
12.3 Initialization and Configuration........................................................................................................... 238
12.4 Register Map ..................................................................................................................................... 239
12.5 Register Descriptions......................................................................................................................... 240
13. Inter-Integrated Circuit (I2C) Interface ............................................................................ 264
13.1 Block Diagram ................................................................................................................................... 264
13.2 Functional Description ....................................................................................................................... 264
13.2.1 I2C Bus Functional Overview ............................................................................................................. 265
13.2.2 Available Speed Modes ..................................................................................................................... 272
13.3 Initialization and Configuration........................................................................................................... 273
13.4 Register Map ..................................................................................................................................... 273
13.5 Register Descriptions (I2C Master).................................................................................................... 274
13.6 Register Descriptions (I2C Slave)...................................................................................................... 288
14. Analog Comparator........................................................................................................... 296
14.1 Block Diagram ................................................................................................................................... 296
14.2 Functional Description ....................................................................................................................... 296
14.2.1 Internal Reference Programming....................................................................................................... 297
14.3 Initialization and Configuration........................................................................................................... 298
14.4 Register Map ..................................................................................................................................... 299
14.5 Register Descriptions......................................................................................................................... 299
15. Pin Diagram ....................................................................................................................... 307
16. Signal Tables ..................................................................................................................... 308
17. Operating Characteristics ................................................................................................ 315
18. Electrical Characteristics ................................................................................................. 316
18.1 DC Characteristics ............................................................................................................................. 316
18.1.1 Maximum Ratings .............................................................................................................................. 316
18.1.2 Recommended DC Operating Conditions ......................................................................................... 316
18.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics .................................................................. 317
18.1.4 Power Specifications ......................................................................................................................... 318
October 6, 2006
Preliminary
5

5 Page





LM3S102 arduino
LM3S102 Data Sheet
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
www.DataSheet4UR.ecogmister 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
GPIO Interrupt Event (GPIOIEV), offset 0x40C....................................................................... 112
GPIO Interrupt Mask (GPIOIM), offset 0x410.......................................................................... 113
GPIO Raw Interrupt Status (GPIORIS), offset 0x414.............................................................. 114
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ........................................................ 115
GPIO Interrupt Clear (GPIOICR), offset 0x41C....................................................................... 116
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ................................................. 117
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500.............................................................. 118
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504.............................................................. 119
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508.............................................................. 120
GPIO Open Drain Select (GPIOODR), offset 0x50C............................................................... 121
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ...................................................................... 122
GPIO Pull-Down Select (GPIOPDR), offset 0x514.................................................................. 123
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518...................................................... 124
GPIO Digital Input Enable (GPIODEN), offset 0x51C ............................................................. 125
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ........................................... 126
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ........................................... 127
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ........................................... 128
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC........................................... 129
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ........................................... 130
GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 ............................................ 131
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ........................................... 132
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC........................................... 133
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .............................................. 134
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .............................................. 135
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .............................................. 136
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC.............................................. 137
General-Purpose Timers .............................................................................................................. 138
Register 1: GPTM Configuration (GPTMCFG), offset 0x000..................................................................... 150
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 .................................................................. 151
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 .................................................................. 152
Register 4: GPTM Control (GPTMCTL), offset 0x00C............................................................................... 153
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .................................................................... 155
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .......................................................... 157
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ..................................................... 158
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024..................................................................... 159
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ...................................................... 160
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C...................................................... 161
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ....................................................... 162
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ....................................................... 163
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038.............................................................. 164
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ............................................................. 165
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040................................................ 166
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044................................................ 167
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................... 168
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C .............................................................................. 169
Watchdog Timer............................................................................................................................ 170
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ............................................................................ 173
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ......................................................................... 174
October 6, 2006
Preliminary
11

11 Page







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