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PDF PI74ALVCH162827 Data sheet ( Hoja de datos )

Número de pieza PI74ALVCH162827
Descripción 20-Bit Buffer Driver
Fabricantes Pericom Semiconductor Corporation 
Logotipo Pericom Semiconductor Corporation Logotipo



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No Preview Available ! PI74ALVCH162827 Hoja de datos, Descripción, Manual

PI74ALVCH162827
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20-Bit Buffer Driver
with 3-STATE Outputs
Product Features
PI74ALVCH162827 is designed for low voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
www.DataShe<et04U.8.cVomat VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Output ports have equivalent 26series resistors;
no external resistors are required
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH162827 is a 20-bit non-inverting buffer/driver
designed for 2.3V to 3.6V VCC operation.
The buffer/driver is composed of two 10-bit sections with separate
output-enable signals. For either 10-bit buffer section, the two
output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must
both be low for the corresponding Y outputs to be active. If either
output-enable input is HIGH, the outputs of that 10-bit buffer
section are in the high-impedance state.
The outputs, which are designed to sink up to 12mA, include 26
resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH162827 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
Logic Block Diagram
1OE1 1
1OE2 56
1A1 55
2 1Y1
To 9 Other Channels
2OE1 28
2OE2 29
2A1 42
15 2Y1
To 9 Other Channels
1 PS8095B 10/07/98

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