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PDF PI74ALVCH162820 Data sheet ( Hoja de datos )
| Número de pieza | PI74ALVCH162820 | |
| Descripción | 3.3V 10-Bit Flip-Flop | |
| Fabricantes | Pericom Semiconductor Corporation | |
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PI74ALVCH162820
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3.3V 10-Bit Flip-Flop with Dual Outputs
and 3-State Outputs
Product Features
• PI74ALVCH162820 is designed for low voltage operation
• VCC=2.3Vto3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
www.DataS•heTety4pUi.ccaolmVOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Output ports have equivalent 26Ω series resistors,
no external resistors are required.
• Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH162820 is a 10-bit flip-flop designed for 2.3V to 3.3V
VCC operation. The PI74ALVCH162820 is designed with edge-
triggered D-type flip-flops. On the positive transition of clock (CLK)
input, the device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a high-
impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capacity to drive bus lines without
the need for interface or pullup components. OE does not affect the
internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance
state.
The outputs, which are designed to sink up to 12mA, include
26Ω resistors to reduce overshoot and undershoot.
The PI74ALVCH162820 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1 PS8094A 03/26/97
1 page  
PI74ALVCH162820
3.3V 10-BIT FLIP-FLOP WITH
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Switching Characteristics over Operating Range(1)
Parameters
From
To VCC = 2.5V ± 0.2V VCC = 2.7V
(INPUT) (OUTPUT) Min.(2)
Max. Min.(2) Max.
VCC = 3.3V ± 0.3V
Min.(2) Max.(2)
Units
fMAX
150 150 150
tPD CLK Q
tEN OE Q
1.0 7.0
1.0 7.4
6.2 1.0
6.8 1.0
5.4
ns
5.6
www.DataSheet4tUD.IcSom
OE
Q
1.3 6.4
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
5.5
1.0
5.0
Operating Characteristics, TA = 25ºC
Parameter
CPD Power Dissipation
Capacitance
Outputs Enabled
Outputs Disabled
Test Conditions
CL = 50pF,
f = 10 MHz
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Typical
68 66
39 47
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5 PS8094A 03/26/97
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PI74ALVCH162820.PDF ] | |
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