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PDF PI74ALVCH16271 Data sheet ( Hoja de datos )
| Número de pieza | PI74ALVCH16271 | |
| Descripción | 12-Bit To 24-Bit Registered Bus Exchanger | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PI74ALVCH16271 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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12-Bit To 24-Bit Multiplexed Bus Exchanger
with 3-State Outputs
Product Features
• PI74ALVCH16271 is designed for low voltage operation,
VCC = 2.3V to 3.6V
• Hysteresis on all inputs
www.DataS•heTeyt4pUic.caolmVOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
56-pin 240 mil wide plastic TSSOP (A56)
56-pin 300 mil wide plastic SSOP (V56)
Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74AVC series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
This 12-bit to 24-bit multiplexed bus exchanger is designed for 2.3V
to 3.6V VCC operation.
The PI74ALVCH16271is intended for applications in which two
separate data paths must be multiplexed onto, or demultiplexed
from, a single data path. This device is particularly suitable as an
interface between conventional DRAMs and high-speed
microprocessors
Data is stored in the internal A-to-B registers on the low-to-high
transition of the clock (CLK) input, provided clock-enable (CLKENA)
inputs are low. Proper control of these inputs allows two sequential
12-bit words to be presented as a 24-bit word on the B port.
To maximize memory access throughput, transparent latches in
the B-to-A path allow asynchronous operation. These latches
transfer data when the latch-enable (LE) inputs are low. The select
(SEL) line selects 1B or 2B data for the A outputs. Data flow is
controlled by the active-low output enables (OEA, OEB).
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor, the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1 PS8360 02/02/99
1 page  
PI74ALVCH16271
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Timing Requirements over Operating Range
Parameters
Description
VCC= 2.5 V ± 0.2 V
Min. Max.
VCC= 2.7 V
Min. Max.
fCLOCK
tW
Clock frequency
Pulse duration,
CLK high or Low
0 130 0 130
3.3 3.3
A before CLK↑
2.6
2.1
tSU Setup time
B before LE
1.7
1.5
www.DataSheet4U.com
CLKEN before CLK↑
A after CLK↑
1.6
0.6
1.3
0.6
tH Hold time
B after LE
CLKEN after CLK↑
0.9
1.0
0.9
0.9
∆t/∆v(1)
Input Transition
Rise or Fall
0 10 0 10
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
VCC= 3.3 V ± 0.3 V
Min.
Max.
0 130
3.3
1.7
1.3
1.0
0.7
1.1
0.9
0 10
Units
Mhz
ns
ns/V
Switching Characteristics over Operating Range(1)
Parameters
From
(INPUT)
To
(OUTPUT)
VCC = 2.5V ± 0.2V
Min.(2)
Max.
VCC = 2.7V
Min.(2) Max.
fMAX
130 130
tPD CLK B 1.0 6.2
5.0
tPD B A 1.0 5.3
4.7
tPD LE A 1.0 6.0
5.9
tPD SEL A 1.1 6.4
6.2
tEN
OEB or OEA
B or A
1.0
6.0
6.1
tDIS
OEB or OEA
B or A
1.4
5.4
4.6
Notes:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
VCC = 3.3V ± 0.3V
Min.(2)
Max.(2)
130
1.0 4.3
1.4 4.0
1.4 4.8
1.3 5.2
1.0 5.1
1.7 4.2
Units
MHz
ns
5 PS8360 02/02/99
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PI74ALVCH16271.PDF ] | |
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