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PDF PI74ALVCH16270 Data sheet ( Hoja de datos )
| Número de pieza | PI74ALVCH16270 | |
| Descripción | 12-Bit To 24-Bit Registered Bus Exchanger | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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PI74ALVCH16270
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PI74ALVCH16270
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12-Bit To 24-Bit Registered Bus Exchanger
with 3-State Outputs
Product Features
• PI74ALVCH16270 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
www.DataS•heTeyt4pUi.ccaolmVOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI7ALVCH16270 is used in applications where data must
be transferred from a narrow high-speed bus to a wider lower
frequency bus.
The device provides synchronous data exchange between the two
ports. Data is stored in the internal registers on the
low-to-high transition of the clock (CLK) input when the appropriate
CLKEN inputs are low. The select (SEL) line selects 1B or 2B
data for the A outputs. For data transfer in the A-to-B direction, a
two stage pipeline is provided in the A-to1B path,with a single
storage register in the A-to-2B path. Proper control of the CLKENA
inputs allows two sequential 12-bit words to be presented
synchronously as a 24-bit on the B port. Data flow is controlled by
the active-low output enables (OEA, OEB). The control terminals
are registered to synchronize the bus direction changes with the
CLK.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor, the
minimum value of the resistor is determined by the current-sinking
capability of the driver. Due to OE being routed through a register,
the active state of the outputs cannot be determined prior to the
arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1 PS8171A 03/05/03
1 page  
PI74ALVCH16270
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Switching Characteristics over Operating Range(1)
Parame te rs
From
To VCC = 2.5V ± 0.2V
(IN PUT) (OUTPUT) M in.(2)
M ax.
VCC = 2.7V
M in.(2) M ax.
150 150
FMAX
C LK
C LK
B
A
2 6.5
1.7 6
5.8
5.4
tPD SEL A 1.9 6.8
6.4
tEN
C LK
A or B
1.6
7.5
www.DataSheet4tUD.IcSom
C LK
A or B
2.6
7.4
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.8
6.5
VCC = 3.3V ± 0.3V
M in.(2)
150
1.1
1
1
1
1.1
M ax.(2)
5.1
4.7
5.5
6
5.8
Units
ns
Operating Characteristics, TA = 25ºC
Parameter
Test Conditions
CPD Power Dissipation
Capacitance
Outputs Enabled
Outputs Disabled
CL = 50pF,
f = 10 MHz
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Typical
87 120
80.5 118
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5 PS8171A 03/05/03
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PI74ALVCH16270.PDF ] | |
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