|
|
PDF ASM4SSTVF16859 Data sheet ( Hoja de datos )
| Número de pieza | ASM4SSTVF16859 | |
| Descripción | DDR 13-Bit to 26-Bit Registered Buffer | |
| Fabricantes | Alliance Semiconductor Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ASM4SSTVF16859 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
August 2004
ASM4SSTVF16859
rev 2.0
DDR 13-Bit to 26-Bit Registered Buffer
Features
Differential clock signals.
Meets SSTL_2 class II specifications on
outputs.
Low voltage operation: VDD = 2.3V to 2.7V.
www.DataSheet4U.com
Available in 64-pin TSSOP, 64-pin TVSOP,
and 56-pin VFQFN packages.
Product Description
The ASM4SSTVF16859 is a universal 13/26 bit
register (D F/F based), designed for 2.3V to 2.7V
VDD operation. The device supports SSTL_2 I/O
levels, and is fully compliant with the JEDEC JC40,
JC42.5 DDR I specifications covering PC1600, PC
2100, PC2700, and PC3200 operational ranges ( DDR
400 – 200 MHz ). 13/26 bits refers to 2Q outputs for
each D input - designed for use in Stacked Registered
(stacked Memory Devices), Buffered DIMM
applications.
Data flow from D to Q is controlled by the differential
clock (CLK/CLKB) and a control signal (RESETB).
The positive edge of CLK is used to trigger the data
transfer, and CLKB is used to maintain sufficient noise
margins, whereas RESETB input is designed and
intended for use at power-up.
The ASM4SSTVF16859 supports a low power standby
mode of operation. A logic level low at RESETB,
assures that all internal registers and outputs (Q) are
reset to a logic low state, and that all input receivers,
data (D) buffers, and clock (CLK/CLKB) are switched
off. Note that RESETB should be supported with a
LVCMOS level at a valid state since VREF may not be
stable during power-up.
To ensure that outputs are at a defined logic state before a
stable clock has been supplied, RESETB must be held at a
logic low level during power-up.
In the JEDEC defined Registered DDR DIMM application,
RESETB is specified to be asynchronous with respect to
CLK/CLKB; therefore, no timing relationship can be
guaranteed between the two signals. When entering a
low-power standby state, the register will be cleared and
the outputs will be driven to a logic low level quickly
relative to the time to disable the differential input
receivers. This ensures there are no “glitches” on any
output. However, when coming out of low power standby
mode, the register will become active quickly relative to the
time taken to enable the differential input receivers. When
the data inputs are at a logic level low and the clock is
stable during the low-to-high transition of RESETB until the
input receivers are fully enabled, the design ensures that
the outputs will remain at a logic low level.
Applications
• JEDEC and Non-JEDEC DDR Memory Modules
• Stacked or Planar configurations.
• Supports PC1600 - PC2100 - PC2700 - PC3200
• DDR 400 compliant (200MHz+).
• SSTL_2 I/O.
• Provides a complete support solution for JEDEC
JC42.5 DIMMs’ when used with the ASM5CVF857
Zero Delay Buffer.
Alliance Semiconductor
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
August 2004
ASM4SSTVF16859
rev 2.0
Truth Table
Inputs
Q Outputs
RESETB
CLK
CLKB
D
Q
L
X or floating
X or floating
X or floating
L
H HH
HL
H
L or H
L or H
X
L
Q02
Note:
www.DataSheet41U. .Hco=mHigh signal level, L=Low signal level, = transition from low to high, = transition from high to low, X = don’t care
2. Output level before the indicated steady state input conditions were established.
1
Absolute Maximum Ratings
Parameter
Min Max Unit
Storage Temperature
-65
+150
°C
Supply Voltage
Input Voltage1
Output Voltage1,2
-0.5 3.6 V
-0.5
VDD + 0.5
V
-0.5
VDD + 0.5
V
Input Clamp Current
± 50 mA
Output Clamp Current
±50 mA
Continuous Output Current
±50 mA
VDD, VDDQ or GND current/pin
Package Thermal Impedance3
100 mA
55 °C/W
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V0 > VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged periods
can affect device reliability.
DDR 13-Bit to 26-Bit Registered Buffer
4 of 16
5 Page 
August 2004
rev 2.0
Timing input
Input
www.DataSheetP4Ur.ocopmagation delay times
Timing input
Output
ASM4SSTVF16859
t
s
V
REF
V
ICR
t
h
V
I(pp)
V
REF
V
IH
V
IL
V
ICR
t
PLH
V
TT
V
ICR
V
I(pp)
t
PHL
V
TT
V
OH
V
OL
LVCMOS RESETB
Input
Output
V /2
DD
t
PHL
V
TT
V
IH
V
IL
V
OH
V
OL
Output slew rates over recommended operating free-air temperature range (unless otherwise noted)
Parameter
From
To
dV/dt_r
dV/dt_f
dV/dt_
20%
80%
80%
20%
20% or 80% 80% or 20%
VCC= 2.5 V + 0.2V *
Min Max
14
14
1
VCC = 2.6 V + 0.1 V *
Min Max
14
14
1
*For this test condition, VDDQ is always equal to VDD
**Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
Unit
V/ns
V/ns
V/ns
DDR 13-Bit to 26-Bit Registered Buffer
10 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ASM4SSTVF16859.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ASM4SSTVF16857 | DDR 14-Bit Registered Buffer | Alliance Semiconductor Corporation |
| ASM4SSTVF16859 | DDR 13-Bit to 26-Bit Registered Buffer | Alliance Semiconductor Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |