|
|
PDF PLL103-02 Data sheet ( Hoja de datos )
| Número de pieza | PLL103-02 | |
| Descripción | DDR SDRAM Buffer | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PLL103-02 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
FEATURES
• Generates 24 output buffers from one input.
• Supports up to four DDR DIMMS.
• Supports 266MHz DDR SDRAM.
• One additional output for feedback.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
• 2.5V Supply range.
www.DataShe•et4U.Econmhanced DDR Output Drive selected by I2C.
• Available in 48 pin SSOP.
BLOCK DIAGRAM
SDATA
SCLK
I2C
Control
BUF_IN
PD#
DDR0T
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DDR3T
DDR3C
DDR4T
DDR4C
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
PIN CONFIGURATION
FBOUT
VDD2.5
GND
DDR0T
DDR0C
DDR1T
DDR1C
VDD2.5
GND
DDR2T
DDR2C
VDD2.5
BUF_IN
GND
DDR3T
DDR3C
VDD2.5
GND
DDR4T
DDR4C
DDR5T
DDR5C
VDD2.5
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note: #: Active Low
48 N/C
47 VDD2.5
46 GND
45 DDR11T
44 DDR11C
43 DDR10T
42 DDR10C
41 VDD2.5
40 GND
39 DDR9T
38 DDR9C
37 VDD2.5
36 PD#
35 GND
34 DDR8T
33 DDR8C
32 VDD2.5
31 GND
30 DDR7T
29 DDR7C
28 DDR6T
27 DDR6C
26 GND
25 SCLK
DESCRIPTION
The PLL103-02 is designed as a 2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 24 outputs. These outputs can be
configured to support four unbuffered DDR DIMMS.
The PLL103-02 can be used in conjunction with a
clock synthesizer for the VIA Pro 266 chipset.
The PLL103-02 also has an I2C interface, which can
enable or disable each output clock. When powered
up, all output clocks are enabled (have internal pull
ups).
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1
1 page  
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
3. Electrical Specifications (Continued)
PARAMETERS SYMBOL
Supply Current
Output Crossing
Voltage
Output Voltage
Swing
Duty Cycle
Max. Operating
www.DataSheeFt4rUe.qcuoemncy
Rising Edge Rate
Falling Edge Rate
Clock Skew ( pin to
pin )
Stabilization Time
IDDS
VOC
VOUT
DT
TOR
TOF
TSKEW
TST
Note: TBM: To be measured
CONDITIONS
PD = 0
Measured @ 1.5V
Measured @
Measured @
0.4V ~ 2.4V
2.4V ~ 0.4V
All outputs equally loaded
MIN.
(VDD/2)
-0.1
1.1
45
66
1.0
1.0
TYP.
VDD/2
50
1.5
1.5
MAX.
TBM
(VDD/2)+
0.1
VDD-0.4
55
170
2.0
2.0
100
0.1
UNITS
mA
V
V
%
MHz
V/ns
V/ns
ps
ms
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PLL103-02.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PLL103-01 | Low Skew Buffer | PhaseLink Corporation |
| PLL103-02 | DDR SDRAM Buffer | PhaseLink Corporation |
| PLL103-03 | DDR SDRAM Buffer | PhaseLink Corporation |
| PLL103-04 | 1-to-4 Clock Distribution Buffer | PhaseLink Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |