|
|
Número de pieza | PLL102-15 | |
Descripción | Low Skew Output Buffer | |
Fabricantes | PhaseLink Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PLL102-15 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! PLL102-15
Low Skew Output Buffer
FEATURES
PIN CONFIGURATION
• Frequency range 25 ~ 60MHz.
• Internal phase locked loop will allow spread spec-
trum modulation on reference clock to pass to the
outputs (up to 33kHz SST modulation).
• Zero input - output delay.
• Less than 700 ps device - device skew.
• Less than 250 ps skew between outputs.
www.DataShee•t4U.Lcoemss than 200 ps cycle - cycle jitter.
• Output Enable function tri-state outputs.
• 3.3V operation.
• Available in 8 -Pin 150mil SOIC.
DESCRIPTIONS
VDD
CLK1
CLKOUT
GND
1
2
3
4
8 N/C
7 CLK3
6 CLK2
5 REF_IN
Remark
If REF_IN clock is stopped for more than 10us after it has already been
provided to the chip, and after power-up, the output clocks will
disappear. In that instance, a full power-up reset is required in order
to reactivate the output clocks.
The PLL102 -15 is a high performance, low skew, low
jitter zero delay buffer designed to distribute high
speed clocks and is available in 8 -pin SOIC or TSSOP
package. It has four outputs that are synchronized with
the input. The synchronization is established via
CLKOUT feedback to the input of the PLL. Since the
skew b etween the input and outpu t is less than ±350
ps, the device acts as a zero delay buffer.
BLOCK DIAGRAM
REF_IN
PLL
CLKOUT
CLK1
CLK2
CLK3
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/06/03 Page 1
1 page SWITCHING WAVE FORMS
All Outputs Rise/Fall Time
Output
www.DataSheet4U.com
2.0V
0.8V
tr
2.0V
0.8V
tf
Input to Output Propagation Delay
VDD/2
Input
Output
VDD/2
Tdelay
PLL102-15
Low Skew Output Buffer
3.3V
0V
Device to Device Skew
VDD/2
Device1 CLKOUT
Device2 CLKOUT
VDD/2
Tdsk - dsk
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/06/03 Page 5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet PLL102-15.PDF ] |
Número de pieza | Descripción | Fabricantes |
PLL102-10 | Low Skew Output Buffer | PhaseLink Corporation |
PLL102-108 | Programmable DDR Zero Delay Clock Driver | PhaseLink Corporation |
PLL102-109 | Programmable DDR Zero Delay Clock Driver | PhaseLink Corporation |
PLL102-15 | Low Skew Output Buffer | PhaseLink Corporation |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |