PDF PLL102-108 Data sheet ( Hoja de datos )

Número de pieza	PLL102-108
Descripción	Programmable DDR Zero Delay Clock Driver
Fabricantes	PhaseLink Corporation
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No Preview Available ! PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES • PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of ten differential outputs. • Track spread spectrum clocking for EMI reduction. • Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming www.DataSheet4UC.cLomKINT and FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled. • Four independent programmable DDR skew chan- nels from –0.3ns to +0.4ns with step size ±100ps. • Support 2-wire I2C serial bus interface. • 2.5V Operating Voltage. • Available in 48-Pin 300mil SSOP. DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AVdd to ground. BLOCK DIAGRAM PIN CONFIGURATION GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT N/C VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 GND 47 CLKC5 46 CLKT5 45 VDD 44 CLKT6 43 CLKC6 42 GND 41 GND 40 CLKC7 39 CLKT7 38 VDD 37 SDATA 36 N/C 35 FB_INT 34 VDD 33 FB_OUTT 32 N/C 31 GND 30 CLKC8 29 CLKT8 28 VDD 27 CLKT9 26 CLKC9 25 GND AV DD CLK_INT Programmable Delay Channel (0~2.5ns) +170ps step FB_INT AV DD Control Logic PLL Programmable Skew Channel -600~+800ps ±200ps step -300~+400ps ±100ps step -300~+400ps ±100ps step -300~+400ps ±100ps step -300~+400ps ±100ps step FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1 CLKT5 CLKC5 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 CLKT6 CLKC6 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 1 1 page PLL102-108 Programmable DDR Zero Delay Clock Driver 4. BYTE 3: Outputs Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 www.DataSheet4U.coBmit 3 Bit 2 Bit 1 Bit 0 Name - Skew FBOUT Bit <2> Bit <1> Bit <0> Bit <3> Delay CLKINT Bit <2> Bit <1> Bit <0> Default Description 1 Reserved 0 These three bits will adjust timing of FBOUTT signal either positive 1 or negative delay up to +800ps or –600ps with ±200ps per step. 1 (see Table 1) 0 0 These four bits will program the propagation delay from CLK_INT to the input of PLL within the range between 0ps and 2.5ns with 0 170ps step size. (see Table 2) 0 TABLE 2: CLK_INT Delay Programming Summary: Bit<3:0> 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 CLK_INT to CLK Delay +2,550 ps +2,380 ps +2,210 ps +2,040 ps +1,870 ps +1,700 ps +1,530 ps +1,360 ps +1,190 ps +1,020 ps +850 ps +680 ps +510 ps +340 ps +170 ps Default 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 5 5 Page

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