|
|
PDF PPC440SPE Data sheet ( Hoja de datos )
| Número de pieza | PPC440SPE | |
| Descripción | Power PC 440EP Embedded Processor | |
| Fabricantes | AMCC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PPC440SPE (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Part Number 440SPe
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
PowerPC 440SPe Embedded Processor
Features
• PowerPC® 440 processor core operating up to
667 MHz with 32KB I- and D-caches (with parity
checking)
• On-chip 256KB SRAM configurable as L2 Cache
www.DataSheet4U.coormEthernet Packet/Code store memory
• Selectable Processor vs Bus clock ratios (Refer to
the Clocking chapter in the PPC440SPe
Embedded Processor User’s Manual for details)
• Support up to 16 GB (4 Chip Selects) of 64-bit/32-
bit SDRAM with ECC
DDR I 266-333-400
DDR II 400-533-667
• Three PCI-Express serial interfaces:
one 8 lanes and two 4 lanes - 2.5Gb/s per lane
Root and Endpoint support.
Opaque bridge
• Optional:16 Programmable Galois Field
polynomials including 14d and 11d
• XOR Accelerator with DMA controller
• I2O messaging with two DMA controllers
• External Peripheral Bus (16-bit Data, 27-bit
Address) for up to three devices; Bank0=16 MB,
Bank1 and Bank2=128 MB each
• One Ethernet 10/100/1000Mbps half- or full-
duplex interface. Operational modes supported
are MII and GMII.
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT)
• Three serial ports (16750 compatible UART)
• One 64-bit DDR PCI-X interfaces up to 133 MHz
(DDR 266) with support for conventional PCI
• Optional: High throughput RAID 6 hardware
acceleration, performs XOR and Galois Field P &
Q parity computations, supports up to 255 drives
• Two IIC interfaces
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• Processor can boot from PCI memory
Description
Designed specifically to address high-end embedded
applications for storage, the PowerPC 440SPe
(PPC440SPe) provides a high-performance, low
power solution that interfaces to a wide range of
peripherals by incorporating on-chip power
management features and lower power dissipation.
This chip contains a high-performance RISC
processor core, a DDR1/DDR2 SDRAM controller,
configurable 256KB SRAM to be used as L2 cache or
software-controlled on-chip memory, three PCI-
Express interfaces, one DDR PCI-X bus interface, a
1Gbps Ethernet interface, an I2O/DMA controller,
control for external ROM and peripherals, optional
RAID 6 acceleration, an XOR DMA unit, serial ports,
IIC interfaces, and general purpose I/O.
Technology: CMOS Cu-11, 0.13mm
Package: 27mm, 675-ball, 1mm pitch, Flip Chip-
Plastic Ball Grid Array (FC-PBGA)
Power (estimated): Less than 14W @533MHz
Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V
AMCC Proprietary
1
1 page  
PowerPC 440SPe Embedded Processor
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
PPC440SPe Functional Block Diagram
Figure 2. PPC440SPe Functional Block Diagram
16 IRQs
Universal
Interrupt
Controller
www.DataSheet4U.com
Clock,
Control,
Reset
Power
Mgmt
Timers
MMU
PPC440 MAC
Processor Core
DCRs
Registers
DCR Bus
JTAG
32 KB
D-Cache
Trace
32 KB
I-Cache
256 KB
L2 Cache/SRAM
PCI-E
IRQ Handler
Processor Local Bus (PLB)
GP
Timers
GPIO
IIC
x2
UART
x3
On-chip Peripheral Bus (OPB)
OPB
Bridge
PLB
Arb
Low Latency (LL) Segment
High Bandwidth (HB) Segment
MAL
Ethernet
10/100/
1000
External
Bus Controller
(EBC)
I2O/DMA
Controller
(DMA0 and
DMA1)
Memory
Queue
DDR 1 and 2
SDRAM Cntl
XOR/DMA
Accelerator
Unit
(DMA2)
PCI-Express
PCI-E0 PCI-E1 PCI-E2
DDR PCI-X
64-bit
MII,
GMII
64+8
8 lanes 4 lanes 4 lanes
16
The PPC440SPe is a System on a Chip (SOC) designed around the IBM CoreConnect Bus™ Architecture.
Implemented with the Crossbar option, the CoreConnect buses provide:
• Two Master PLB bus 128-bit Data 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the
Read and Write data path (10.6 GB/s total)
• 32-bit OPB interfaces up to 83.33MHz for a maximum throughput of 333MB/s
AMCC Proprietary
5
5 Page 
PowerPC 440SPe Embedded Processor
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
• Buffering in each PCI Express Port for the following transaction types:
– 4K byte Replay buffer: up to 8 in flight transactions
– 2K bytes for Outbound posted Writes
– 8K bytes for Outbound Reads completion
• 2K prefetch request from first I2O/DMA PLB Master
• 1K prefetch request from 2nd I2O/DMA PLB Master
• 1K prefetch request from first PCIE 4x links
• 1K prefetch request from 2nd PCIE 4x links
• 256 byte from the PPC440
– 2K bytes for Inbound posted Writes
– 2K bytes for Inbound Reads completion
www.DataSheet4•U.cPoamrity checking on each buffer
• POM Programmable Outbound Memory Regions: 3 Memory, 1 I/O, 1 Message, 1 config, 1 Internal Regs
• PIM Programmable Inbound Memory Regions: 4 Memory, 1 I/O, 1 Expansion ROM
• INTx Interrupts support (PCI legacy):
– up to 4 INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC
– A/B/C/D INTx types Generation for Endpoints
• MSI - Message Signaled Interrupts
– MSI Generation for End Point
– MSI Termination for Root Ports
– MSI_X Termination for Root Ports
DDR PCI-X Interface
The DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local
memory. The PCI-X interface supports 64-bit PCI-X bus in DDR mode 2. It can be configured for either host or
adapter mode. PCI 32/64-bit legacy mode, compatible with PCI Version 2.3, is also supported.
Features include:
• PCI-X 2.0
– Split transactions
– Frequency to 266MHz
– 32- and 64-bit address/data bus
– ECC supported for 266MHz Mode 2 only
• PCI 2.3 backward compatibility
– Frequency to 66MHz
– 32- and 64-bit bus
• Can be the PCI Host Bus Bridge or an Adapter Device PCI interface
• Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can
be disabled for use with an external arbiter
• Support for PLB-based (external to PLB–PCI-X bridge) I2O
• Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management Version 1.1
• PCI arbitration function with PCI-X Mode 2 support (optional)
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI-X bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (Type 0 and Type 1)
– Single beat special cycles
AMCC Proprietary
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PPC440SPE.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PPC440SP | Power PC 440EP Embedded Processor | AMCC |
| PPC440SPE | Power PC 440EP Embedded Processor | AMCC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |