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PDF PPC440SP Data sheet ( Hoja de datos )
| Número de pieza | PPC440SP | |
| Descripción | Power PC 440EP Embedded Processor | |
| Fabricantes | AMCC | |
| Logotipo |  |
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Part Number 440SP
Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Features
• PowerPC‚ 440 processor core operating at up to
667MHz with 32-KB I- and D-caches (with parity
checking)
• On-chip 256-KB SRAM configurable as L2 Cache
www.DataSheet4U.coormEthernet Packet/Code store memory
• Selectable Processor:Bus clock ratios (Refer to
the Clocking chapter in the PPC440SP Embedded
Processor User’s Manual for details)
• Supports up to 4 GB (2 Chip Selects) of 64-bit/32-
bit SDRAM with ECC
– DDR1 266-333-400
– DDR2 400-533-667
• Three DDR PCI-X interfaces (32-bit or 64-bit) up
to 133 MHz (DDR 266) with support for
conventional PCI
• XOR Accelerator with DMA controller
• Optional: High throughput RAID 6 hardware
acceleration, performs XOR and Galois Field P &
Q parity computations, supports up to 255 drives
• I2O Messaging Unit with two DMA controllers
• External Peripheral Bus (24-bit Address, 8-bit
Data) for up to three devices
• One Ethernet 10/100/1000 Mbps half- or full-
duplex interface. Operational modes supported
are MII and GMII.
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT)
• Three serial ports (16750 compatible UART)
• Two IIC interfaces
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• Processor can boot from PCI memory
Description
Designed specifically to address high-end embedded
applications for storage, the PowerPC 440SP
Embedded Processor (PPC440SP) provides a high-
performance, low power solution that interfaces to a
wide range of peripherals by incorporating on-chip
power management features and lower power
dissipation.
This chip contains a high-performance RISC
processor core, a DDR2 SDRAM controller,
configurable 256KB SRAM to be used as L2 cache or
software-controlled on-chip memory, three DDR PCI-X
bus interfaces, an Ethernet interface, an I2O/DMA
controller, control for external ROM and peripherals,
optional RAID 6 acceleration, an XOR DMA unit, serial
ports, IIC interfaces, and general purpose I/O.
Technology: CMOS Cu-11, 0.13mm
Package: 29mm, 783-ball, 1mm pitch, Flip Chip-
Plastic Ball Grid Array (FC-PBGA)
Power (estimated): Less than 6W @533MHz
Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V
AMCC Proprietary
1
1 page  
Revision 1.23 - Sept 26, 2006
Data Sheet
PPC440SP Functional Block Diagram
PowerPC 440SP Embedded Processor
Figure 2. PPC440SP Functional Block Diagram
Universal
Interrupt
Controller
www.DataSheet4U.com
Clock,
Control,
Reset
Power
Mgmt
Timers
MMU
PPC440
Processor Core
JTAG
32 KB
D-Cache
Trace
32 KB
I-Cache
L2 Cache/SRAM
DCRs
DCR Bus
GPT
GPIO
IIC1
IIC0
UART2
UART1
UART0
On-chip Peripheral Bus (OPB)
OPB
Bridge
Processor Local Bus (PLB)
Low Latency (LL) Segment
High Bandwidth (HB) Segment
MAL
I2O/DMA
Controller
(DMA0 and
DMA1)
Memory
Queue
DDR2 SDRAM
Controller
XOR/DMA
Accelerator
Unit
(DMA2)
DDR PCI-X
PCI0 PCI1 PCI2
Host Local Local
64 bits 64 bits 32 bits
PLB
Arbiter
Ethernet
10/100/
1000
(EMAC)
External
Bus Controller
(EBC)
MII,
GMII
The PPC440SP is a System on a chip, which uses IBM® CoreConnect Bus™ Architecture.
Implemented with the Crossbar option, the IBM CoreConnect buses provide:
• 128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data
paths (10.6GB/sec total)
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various processor accessible address regions. The second address
map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the
PPC440SP processor through the use of mtdcr and mfdcr instructions.
AMCC Proprietary
5
5 Page 
Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
• PCI Power Management Version 1.1
• PCI arbitration function with PCI-X Mode 2 support (optional)
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI-X bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces:
– Single beat I/O reads and writes
– Single beat and burst memory reads and writes
– Single beat configuration reads and writes (Type 0 and Type 1)
– Single beat special cycles
• PCI-X initialization sequence support (frequency & mode determination)
www.DataSheet4•U.cSoumpport for unexpected split completions
• Outbound transaction split discard timers
• Vital Product Data (VPD) support
• PCI-to-PCI opaque bridge
DDR1/DDR2 SDRAM Memory Controller
The DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete
devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The
DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high-
speed 1KB FIFO buffers.
Features include:
• Registered and non-registered industry standard DIMMs
• DDR1 266-333-400
• DDR2 400-533-667
• 64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
• 5.32GB/s peak bandwidth for the 64-bit interface
• 2.66GB/s peak bandwidth for the 32-bit interface
• Two chip (bank) select signals supporting two external banks
• CAS latencies of 2, 3, 4, 5, 6, and 7 supported
• Page mode accesses (up to 32 open pages) with configurable paging policy
• Look-ahead request queue with programmable depth of four commands.
• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current
bank)
• Up to 4GB in two external banks
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Sync DRAM configuration by means of mode register and extended mode register set commands
• Power management (self-refresh, suspend, sleep)
• Low Latency & High Bandwidth PLB ports
• Selectable PLB read response (immediate or deferred)
• Programmable Low Latency & High Bandwidth arbitration schemes
• High Bandwidth port has four 1KB read buffers and two1KB write buffers
• Low Latency port has four 128B read buffers and two 128B write buffers
External Peripheral Bus Controller (EBC)
Features include:
• Support 2MB Boot ROM
• Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported
• Burst and non-burst devices
• 8-bit data bus
AMCC Proprietary
11
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| PDF Descargar | [ Datasheet PPC440SP.PDF ] | |
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