PDF CY28447 Data sheet ( Hoja de datos )

Número de pieza	CY28447
Descripción	Clock Generator
Fabricantes	ETC
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No Preview Available ! www.DataSheet4U.com PRELIMINARY CY28447 Clock Generator for Intel® Calistoga Chipset Features • Compliant to Intel® CK410M • Selectable CPU frequencies • Differential CPU clock pairs • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 27 MHz Spread and Non-spread video clock • 48 MHz USB clock • SRC clocks independently stoppable through CLKREQ#[1:9] • 96/100 MHz spreadable differential video clock Block Diagram • 33 MHz PCI clocks • Buffered Reference Clock 14.318MHz • Low-voltage frequency select inputs • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 72-pin QFN package CPU x2 / x3 SRC x9/11 PCI REF DOT96 USB_48M x5 x 2 x 1 x1 LCD x1 27M x2 Pin Configuration XIN XOUT SEL_CLKREQ PCI_STP# CPU_STP# CLKREQ[1:9]# ITP_SEL FS[C:A] 14.318MHz Crystal PLL Reference CPU PLL Divider FCTSEL1 VTT_PWRGD#/PD SDATA SCLK LVDS PLL Divider Fixed PLL Divider 27M PLL I2C Logic Divider VDD REF[1:0] IREF VDD CPUT[0:1] CPUC[0:1] VDD CPUT2_ITP/SRCT10 CPUC2_ITP/SRCC10 VDD SRCT(1:9]) SRCC(1:9]) VDD PCI[1:4] VDD_PCI PCIF0 VDD SRCT0/100MT_SST SRCC0/100MC_SST VDD48 27MSpread VDD48 DOT96T DOT96C VDD48 48M VDD48 27MNon-spread VDD_SRC SRCC_9 SRCT_9 VSS_SRC CPUC2_ITP / SRCC_10 CPUT2_ITP / SRCT_10 VDDA VSSA IREF CPUC1 CPUT1 VDD_CPU CPUC0 CPUT0 VSS_CPU SCLK SDATA VDD_REF 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 CY28447 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD_SRC SRCC_2 SRCT_2 SRCC_1 SRCT_1 VDD_SRC SRCC_0 / LCD100MC SRCT_0 / LCD100MT CLKREQ1# FSB/TEST_MODE DOT96C / 27M_SS DOT96T / 27M_NSS VSS_48 48M / FSA VDD_48 VTT_PWRGD# / PD CLKREQ7# PCIF0/ITP_SEL Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 21 www.SpectraLinear.com 1 page CY28447 Control Registers Byte 0: Control Register 0 Bit @Pup 71 Name SRC[T/C]7 61 SRC[T/C]6 51 SRC[T/C]5 41 SRC[T/C]4 31 SRC[T/C]3 21 SRC[T/C]2 11 SRC[T/C]1 01 SRC[T/C]0 /LCD_96_100M[T/C] Description SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]0 / LCD_96_100M[T/C] Output Enable 0 = Disable (Hi-Z), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name Description 71 PCIF0 PCIF0 Output Enable 0 = Disabled, 1 = Enabled 6 1 27M NSS / DOT_96[T/C] 27M Non-spread and DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled 51 USB_48MHz USB_48M MHz Output Enable 0 = Disabled, 1 = Enabled 41 REF0 REF0 Output Enable 0 = Disabled, 1 = Enabled 31 REF1 REF1 Output Enable 0 = Disabled, 1 = Enabled 21 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled 11 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled 0 0 CPU, SRC, PCI, PCIF PLL1 (CPU PLL) Spread Spectrum Enable Spread Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup 71 61 51 41 31 21 11 01 Name PCI4 PCI3 PCI2 PCI1 Reserved Reserved CPU[T/C]2 Reserved Description PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled Reserved, Set = 1 Reserved, Set = 1 CPU[T/C]2 Output Enable 0 = Disabled (Hi-Z), 1 = Enabled Reserved, Set = 1 Rev 1.0, November 20, 2006 Page 5 of 21 5 Page CY28447 PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthe- sizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must be held HIGH or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock outputs are held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff clock#” tri-state. If the control register PD drive mode PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tri-state. Note that Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, and 200 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 μs after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 μs of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 4. Power-down Assertion Timing Waveform Tstable <1.8 ms PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF Tdrive_PWRDN# <300 μs, >200 mV Figure 5. Power-down Deassertion Timing Waveform Rev 1.0, November 20, 2006 Page 11 of 21 11 Page

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