PDF CY28442 Data sheet ( Hoja de datos )

Número de pieza	CY28442
Descripción	Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com ADVANCE INFORMATION CY28442 Clock Generator for Intel Alviso Chipset Features • Compliant to Intel CK410M • Supports Intel Pentium-M CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 96-MHz differential dot clock • 48-MHz USB clocks • SRC clocks independently stoppable through CLKREQ#[A:B] • 96/100 MHz Spreadable differential clock. • 33-MHz PCI clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin TSSOP package CPU SRC PCI REF DOT96 USB_48 x2 / x3 x5/6 x6 x2 x2 x1 Block Diagram XIN XOUT PCI_STP# CPU_STP# CLKREQ[A:B]# FS_[C:A] 14.318MHz Crystal PLL Reference PLL1 CPU Divider VTTPWR_GD#/PD PLL2 96MSS Divider PLL4 FIXED Divider SDATA SCLK I2C Logic Pin Configuration VDD_REF REF IREF VDD_CPU CPUT CPUC VDD_CPU CPUT_ITP/SRCT7 CPUC_ITP/SRCC7 VDD_SRC SRCT[1:5] CPUC[1:5] VDD_PCI PCI VDD_PCI PCIF VDD_48MHz 96_100_SSCT 96_100_SSCC VDD_48MHz DOT96T DOT96C VDD_48 USB VDD_REF VSS_REF PCI3 PCI4 PCI5 VSS_PCI VDD_PCI ITP_EN/PCIF0 96_100_SEL/PCIF1 VTTPWRGD#/PD VDD_48 FS_A/48M_0 VSS_48 DOT96T DOT96C FS_B/TESTMODE 96_100_SSCT 96_100_SSCC SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRCT4_SATA SRCC4_SATA VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 PCI2/SEL_CLKREQ 55 PCI_STP# 54 CPU_STP# 53 FS_C(TEST_SEL)/REF0 52 REF1 51 VSSA2 50 XIN 49 XOUT 48 VDDA2 47 SDATA 46 SCLK 45 VSS_CPU 44 CPUT0 43 CPUC0 42 VDD_CPU 41 CPUT1 40 CPUC1 39 IREF 38 VSSA 37 VDDA 36 CPU2T_ITP/SRCT7 35 CPU2C_ITP/SRCC7 34 VDD_SRC_ITP 33 CLKREQA#/SRCT6 32 CLKREQB#/SRCC6 31 SRCT5 30 SRCC5 29 VSS_SRC 56 pin TSSOP/SSOP Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07680 Rev. Revised June 24, 2004 1 page ADVANCE INFORMATION Control Registers Byte 0: Control Register 0 Bit @Pup Name 7 1 CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 61 SRC[T/C]6 51 SRC[T/C]5 41 SRC[T/C]4 31 SRC[T/C]3 21 SRC[T/C]2 11 SRC[T/C]1 01 Byte 1: Control Register 1 Bit @Pup 71 RESERVED Name PCIF0 61 DOT_96T/C 51 USB_48 41 REF0 31 REF1 21 CPU[T/C]1 11 CPU[T/C]0 00 CPU Byte 2: Control Register 2 Bit @Pup 71 61 51 41 31 21 11 01 Name PCI5 PCI4 PCI3 PCI2 Reserved Reserved Reserved PCIF1 Description CPU[T/C]2_ITP/SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable RESERVED Description PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled REF1 Output Enable 0 = Disabled, 1 = Enabled CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled Description Document #: 38-07680 Rev. CY28442 Page 5 of 22 5 Page ADVANCE INFORMATION CY28442 CLK_REQ[0:1]# Description The CLKREQ#[A:B] signals are active low input used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ#[A:B] are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that it’s state must remain unchanged during two consec- utive rising edges of SRCC to be recognized as a valid assertion or de-assertion. (The assertion and de-assertion of this signal is absolutely asynchronous). CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between 2-6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] de-assertion to a voltage greater than 200mV. CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ#[A:B] pins is all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ#[A:B] are to be stopped after their next transition. The final state of all stopped DIF signals is low, both SRCT clock and SRCC clock outputs will not be driven. PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual function pin. During initial power up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthe- sizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, all clocks need to be driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) – Assertion When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must held high or Tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition within 4 clock periods. When the SMBus PD drive mode bit corre- sponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tristate. Note the example below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100,133,166,200,266,333 and 400MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 uS after asserting Vtt_PwrGd#. Document #: 38-07680 Rev. ** Page 11 of 22 11 Page

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