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PDF MC13203 Data sheet ( Hoja de datos )
| Número de pieza | MC13203 | |
| Descripción | (MC13202 / MC13203) 2.4 GHz Low Power Transceiver | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC13203 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Freescale Semiconductor
Technical Data
Document Number: MC13202
Rev. 0.0, 03/2006
MC13202/203
MC13202/203
2.4 GHz Low Power Transceiver
for the IEEE® 802.15.4 Standard
Package Information
Plastic Package
Case 1311-03
Ordering Information
Device
MC13202
MC13203
Device Marking
13202
13203
Package
QFN-32
QFN-32
1 Introduction
Thewww.DataSheet4U.com MC13202 and MC13203 are short range, low
power, 2.4 GHz Industrial, Scientific, and Medical
(ISM) band transceivers. The MC13202/MC13203
contain a complete 802.15.4 physical layer (PHY)
modem designed for the IEEE® 802.15.4 wireless
standard which supports peer-to-peer, star, and mesh
networking.
The MC13202 includes the 802.15.4 PHY/MAC for use
with the HCS08 Family of MCUs. The MC13203 also
includes the 802.15.4 PHY/MAC plus the ZigBee
Protocol Stack for use with the HCS08 Family of MCUs.
With the exception of the addition of the ZigBee Protocol
Stack, the MC13203 functionality is the same as the
MC13202.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4
4 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 6
5 Electrical Characteristics . . . . . . . . . . . . . . . 8
6 Functional Description . . . . . . . . . . . . . . . . 11
7 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 14
8 Crystal Oscillator Reference Frequency . . 18
9 Transceiver RF Configurations and
External Connections . . . . . . . . . . . . . . . . . 21
10Packaging Information . . . . . . . . . . . . . . . . 28
When combined with an appropriate microcontroller
(MCU), the MC13202/MC13203 provides a
cost-effective solution for short-range data links and
networks. Interface with the MCU is accomplished using
a four wire serial peripheral interface (SPI) connection
and an interrupt request output which allows for the use
of a variety of processors. The software and processor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
1 page  
MC13202/MC13203
Analog
Receiv er
Frequency
Generation
Analog
Transmitter
Voltage
Regulators
Pow er Up
Management
Control
Logic
SPI
and GPIO
Buffer RAM
Microcontroller
SPI
ROM
(Flash)
RAM
CPU
Application
Netw ork
MAC
PHY Driv er
A/D
Figure 2. System Level Block Diagram
4 Data Transfer Modes
The MC13202/MC13203 has two data transfer modes:
1. Packet Mode — Data is buffered in on-chip RAM
2. Streaming Mode — Data is processed word-by-word
The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary
applications, packet mode can be used to conserve MCU resources.
4.1 Packet Structure
Figure 3 shows the packet structure of the MC13202/MC13203. Payloads of up to 125 bytes are supported.
The MC13202/MC13203 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a
one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and
appended to the end of the data.
4 bytes
1 byte
Preamble SFD
1 byte
FLI
125 bytes maximum
Payload Data
2 bytes
FCS
Figure 3. MC13202/MC13203 Packet Structure
4.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
Freescale Semiconductor
MC13202/203 Technical Data, Rev. 0.0
5
5 Page 
6 Functional Description
6.1 MC13202/MC13203 Operational Modes
The MC13202/MC13203 has a number of operational modes that allow for low-current operation.
Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is
used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are
summarized, along with the transition times, in Table 6. Current drain in the various modes is listed in
Table 3, DC Electrical Characteristics.
Table 6. MC13202/MC13203 Mode Definitions and Transition Times
Mode
Definition
Transition Time
To or From Idle
Off All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated
including IRQ
10 - 25 ms to Idle
Hibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is 7 - 20 ms to Idle
retained.
Doze
Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = (300 + 1/CLKO) µs to Idle
1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can
be programmed to enter Idle Mode through an internal timer comparator.
Idle Crystal Reference Oscillator On with CLKO output available. SPI active.
Receive Crystal Reference Oscillator On. Receiver On.
144 µs from Idle
Transmit Crystal Reference Oscillator On. Transmitter On.
144 µs from Idle
6.2 Serial Peripheral Interface (SPI)
The host microcontroller directs the MC13202/MC13203, checks its status, and reads/writes data to the
device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction
between the host and the MC13202/MC13203 occurs as multiple 8-bit bursts on the SPI. The SPI signals
are:
1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13202/MC13203. Data is
clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data
out changes state on the trailing (falling) edge of SPICLK.
NOTE
For Freescale microcontrollers, the SPI clock format is the clock phase
control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
4. Master In/Slave Out (MISO) - The MC13202/MC13203 presents data to the master on the MISO
output.
Freescale Semiconductor
MC13202/203 Technical Data, Rev. 0.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MC13203.PDF ] | |
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