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PDF MC13201 Data sheet ( Hoja de datos )
| Número de pieza | MC13201 | |
| Descripción | 2.4 GHz Low Power Transceiver | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Technical Data
Document Number: MC13201
Rev. 1.0, 10/2006
MC13201
MC13201
2.4 GHz Low Power Transceiver
for the IEEE® 802.15.4 Standard
Package Information
Plastic Package
Case 1311-03
QFN -32
Ordering Information
Device
MC13201
Device Marking
13201
Package
QFN-32
1 Introduction
The MC13201 is a short range, low power, 2.4 GHz
Industrial, Scientific, and Medical (ISM) band
transceivers. The MC13201 contains a complete packet
data modem which is compliant with the IEEE®
802.15.4 Standard PHY (Physical) layer. This allows the
development of proprietary point-to-point and star
networks based on the 802.15.4 packet structure and
modulation format. For full 802.15.4 Standard
compliance, the MC13202/203 and Freescale's 802.15.4
MAC software are required.
When combined with an appropriate microcontroller
(MCU), the MC13201 provides a cost-effective solution
for short-range data links and networks. Interface with
the MCU is accomplished using a four wire serial
peripheral interface (SPI) connection and an interrupt
request output which allows for the use of a variety of
processors. The software and processor can be scaled to
fit applications ranging from simple point-to-point
systems to star networks.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4
4 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . 5
5 Electrical Characteristics . . . . . . . . . . . . . . . 7
6 Functional Description . . . . . . . . . . . . . . . . 10
7 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 13
8 Crystal Oscillator Reference Frequency . . 17
9 Packaging Information . . . . . . . . . . . . . . . . . 25
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
1 page  
4 Data Transfer Mode
The MC13201 has a data transfer mode called Packet Mode where data is buffered in on-chip Packet
RAMs. There is a TX Packet RAM and an RX Packet RAM, each of which are 64 locations by 16 bits
wide.
4.1 Packet Structure
Figure 3 shows the packet structure of the MC13201 which is consistent with the 802.15.4 Standard.
Payloads of up to 125 bytes are supported. The MC13201 adds a four-byte preamble, a one-byte Start of
Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A Frame Check
Sequence (FCS) is calculated and appended to the end of the data.
4 bytes
1 byte
Preamble SFD
1 byte
FLI
125 bytes maximum
Payload Data
2 bytes
FCS
Figure 3. MC13201 Packet Structure
4.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital backend performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
The MC13201 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet
RAM. The MCU is notified that an entire packet has been received via an interrupt.
Figure 4 shows CCA reported power level versus input power. Note that CCA reported power saturates at
about -57 dBm input power which is well above 802.15.4 Standard requirements. Figure 5 shows energy
detection/LQI reported level versus input power.
NOTE
For both graphs, the required 802.15.4 Standard accuracy and range limits
are shown. A 3.5 dBm offset has been programmed into the CCA reporting
level to center the level over temperature in the graphs.
Freescale Semiconductor
MC13201 Technical Data, Rev. 1.0,
5
5 Page 
6.2 Serial Peripheral Interface (SPI)
The host microcontroller directs the MC13201, checks its status, and reads/writes data to the device
through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between
the host and the MC13201 occurs as multiple 8-bit bursts on the SPI. The SPI signals are:
1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A
transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.
2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13201. Data is clocked into the
master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes
state on the trailing (falling) edge of SPICLK.
NOTE
For Freescale microcontrollers, the SPI clock format is the clock phase
control bit CPHA = 0 and the clock polarity control bit CPOL = 0.
3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.
4. Master In/Slave Out (MISO) - The MC13201 presents data to the master on the MISO output.
A typical interconnection to a microcontroller is shown in Figure 7.
MCU MC13201
Shift Register
Baud Rate
Generator
RxD
TxD
Sclk
Chip Enable (CE)
MISO
MOSI
SPICLK
CE
Shift Register
Figure 7. SPI Interface
Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock
(CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers to internal
registers and memory.
6.2.1 SPI Burst Operation
The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master
(MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the
master on the MISO line. Although an MC13201 transaction is three or more SPI bursts long, the timing
of a single SPI burst is shown in Figure 8.
Freescale Semiconductor
MC13201 Technical Data, Rev. 1.0,
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MC13201.PDF ] | |
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