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PDF MC74VHC138 Data sheet ( Hoja de datos )
| Número de pieza | MC74VHC138 | |
| Descripción | 3-To-8 Line Decoder | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74VHC138
3--to--8 Line Decoder
The MC74VHC138 is an advanced high speed CMOS 3--to--8
decoder fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 -- A2)
determine which one of the outputs (Y0 -- Y7) will go Low. When
enable input E3 is held Low or either E2 or E1 is held High, decoding
function is inhibited and all outputs go high. E3, E2, and E1 inputs are
provided to ease cascade connection and for use as an address decoder
for memory systems.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
• High Speed: tPD = 5.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
www.DataSheet4U.com
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
• These devices are available in Pb--free package(s). Specifications herein
apply to both standard and Pb--free devices. Please see our website at
www.onsemi.com for specific Pb--free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
http://onsemi.com
MARKING DIAGRAMS
SOIC--16
D SUFFIX
CASE 751B
16 9
VHC138
AWLYYWW
18
16 9
TSSOP--16
DT SUFFIX
CASE 948F
VHC
138
AWLYWW
18
16 9
SOIC EIAJ--16
M SUFFIX
CASE 966
1
VHC138
ALYW
8
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC138D
SOIC--16 48 Units/Rail
MC74VHC138DR2 SOIC--16 2500 Units/Reel
MC74VHC138DT TSSOP--16 96 Units/Rail
MC74VHC138DTR2
MC74VHC138M
MC74VHC138MEL
TSSOP--16
SOIC
EIAJ--16
SOIC
EIAJ--16
2500 Units/Reel
48 Units/Rail
2000 Units/Reel
© Semiconductor Components Industries, LLC, 2006
March, 2006 -- Rev. 4
1
Publication Order Number:
MC74VHC138/D
1 page  
MC74VHC138
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VIH Minimum High--Level
Input Voltage
Test Conditions
VIL Maximum
Low--Level Input
Voltage
VOH
VOL
IIN
ICC
Minimum High--Level
Output Voltage
VIN = VIH or VIL
Maximum
Low--Level Output
Voltage
VIN = VIH or VIL
Maximum Input
Leakage Current
VIN = VIH or VIL
IOH = -- 50 μA
VIN = VIH or VIL
IOH = --4 mA
IOH = --8 mA
VIN = VIH or VIL
IOL = 50 μA
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
VIN = 5.5 V or
GND
Maximum Quiescent VIN = VCC or GND
Supply Current
VCC
(V)
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
0 to
5.5
5.5
TA = 25°C
Min Typ Max
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
1.9 2.0
2.9 3.0
4.4 4.5
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
± 0.1
4.0
TA = ≤ 85°C
Min Max
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
± 1.0
40.0
TA = ≤ 125°C
Min Max
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
1.9
2.9
4.4
Unit
V
V
V
2.34
3.66
0.1 V
0.1
0.1
0.52
0.52
± 1.0
μA
40.0 μA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbo
l
tPLH,
tPHL
Parameter
Maximum
Propagation Delay,
A to Y
tPLH,
tPHL
Maximum
Propagation Delay,
E3 to Y
tPLH,
tPHL
Maximum
Propagation Delay,
E2 or E1 to Y
CIN Maximum Input
Capacitance
Test Conditions
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
TA = 25°C
Min Typ Max
8.2 11.4
10.0 15.8
5.7 8.1
7.2 10.1
8.1 12.8
10.6 16.3
5.6 8.1
7.1 10.1
8.2 11.4
10.7 14.9
5.8 8.1
7.3 10.1
4 10
TA = -- 40 to
85°C
Min Max
1.0 13.5
1.0 18.0
1.0 9.5
1.0 11.5
1.0 15.0
1.0 18.5
1.0 9.5
1.0 11.5
1.0 13.5
1.0 17.0
1.0 9.5
1.0 11.5
10
TA = -- 55 to
125°C
Min Max
1.0 13.5
1.0 18.0
1.0 9.5
1.0 11.5
1.0 15.0
1.0 18.5
1.0 9.5
1.0 11.5
1.0 13.5
1.0 17.0
1.0 9.5
1.0 11.5
10
Unit
ns
ns
ns
pF
Typical @ 25°C, VCC = 5.0V
CPD Power Dissipation Capacitance (Note 1)
34 pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current
power consumption; PD =
can be obtained
CPD ¯ VCC2 ¯ fin
by the
+ ICC
equation:
¯ VCC.
ICC(OPR)
=
CPD
¯
VCC
¯
fin
+
ICC.
CPD
is
used
to
determine
the
no--
load
dynamic
http://onsemi.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74VHC138.PDF ] | |
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