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PDF MC74VHC138 Data sheet ( Hoja de datos )
| Número de pieza | MC74VHC138 | |
| Descripción | 3-to-8 Line Decoder | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74VHC138 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3-to-8 Line Decoder
The MC74VHC138 is an advanced high speed CMOS 3–to–8 decoder
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 – A2)
determine which one of the outputs (Y0 – Y7) will go Low. When enable input
E3 is held Low or either E2 or E1 is held High, decoding function is inhibited
and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade
connection and for use as an address decoder for memory systems.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 5.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
FUNCTION TABLE
Inputs
Outputs
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H XXX HHH HHHH H
X H X XXX HHH HHHH H
L X X XXX HHH HHHH H
H L L LLL LHHHHHHH
H L L LLHH L HHHHHH
H L L LHL HH L HHHHH
H L L LHH H H H L H H H H
H L L HLL HHHH L HHH
H L L HLHHHHHH L HH
H L L HHL H H H H H H L H
H L L HHH H H H H H H H L
H = high level (steady state); L = low level (steady state);
X = don’t care
SELECT
INPUTS
A0 1
A1 2
A2 3
ENABLE
INPUTS
E3 6
E2 5
E1 4
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10
Y5
9 Y6
7
Y7
ACTIVE–LOW
OUTPUTS
LOGIC DIAGRAM
MC74VHC138
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01
ORDERING INFORMATION
MC74VHCXXXD
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
PIN ASSIGNMENT
A0 1
A1 2
A2 3
E1 4
E2 5
E3 6
Y7 7
GND 8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
6/97
© Motorola, Inc. 1997
1
REV 1
1 page  
A
tPLH
Y
VALID
50%
50% VCC
SWITCHING WAVEFORMS
VALID
tPHL
VCC
GND
E3
tPHL
Y
50%
50% VCC
Figure 1.
Figure 2.
MC74VHC138
VCC
GND
tPLH
E2 or E1 50%
Y
tPHL
50% VCC
Figure 3.
VCC
GND
tPLH
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
5
MOTOROLA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC74VHC138.PDF ] | |
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