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PDF SI550 Data sheet ( Hoja de datos )
| Número de pieza | SI550 | |
| Descripción | VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR | |
| Fabricantes | SILABS | |
| Logotipo |  |
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Si550
PRELIMINARY DATA SHEET
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)
10 MHZ TO 1.4 GHZ
Features
Available with any-rate output
frequencies from 10 MHz to
945 MHz and selected frequencies
to 1.4 GHz
3rd generation DSPLL® with
superior jitter performance
3x better frequency stability than
SAW based oscillators
Applications
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, & CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Lead-free/RoHS-compliant
SONET / SDH
xDSL
10 GbE LAN / WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to
provide a low-jitter clock at high frequencies. The Si550 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike traditional VCXO’s where a different crystal is required for
each output frequency, the Si550 uses one fixed crystal to provide a wide
range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems. The Si550 IC-based VCXO is
factory configurable for a wide variety of user specifications, including
frequency, supply voltage, output format, tuning slope, and temperature
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
Functional Block Diagram
Si5602
Ordering Information:
See page 8.
Pin Assignments:
See page 7.
(Top View)
VC 1
OE 2
GND 3
6 VDD
5 CLK–
4 CLK+
VDD CLK– CLK+
Fixed
Frequency
XO
Any-rate
10-1400 MHz
DSPLL®
Clock Synthesis
ADC
Vc OE GND
Preliminary Rev. 0.3 4/06
Copyright © 2006 by Silicon Laboratories
Si550
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
1 page  
Si550
Table 6. CLK± Output Period Jitter
Parameter
Symbol
Test Condition
Period Jitter*
for FOUT < 160 MHz
JPER
RMS
Peak-to-Peak
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.
Min
—
—
Table 7. CLK± Output Phase Noise (Typical)
Configuration
Offest Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
fC
KV
Output
74.25 MHz
45 ppm/V
CMOS
300 MHz
90 ppm/V
LVPECL
L (f)
–94
–117
–128
–135
–138
–143
n/a
–74
–98
–112
–122
–134
–144
–147
Typ Max Units
2 — ps
14 —
622.08 MHz
45 ppm/V
LVPECL
Units
–77
–101
–114
–118
–128
–144
–147
dBc/Hz
Preliminary Rev. 0.3
5
5 Page 
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Updated 1. "Electrical Specifications" on page 2.
Updated ordering and format of Table 1 through Table 9.
Updated LVDS and CML in Table 4, “CLK± Output
Levels and Symmetry,” on page 3.
Updated RMS jitter values in Table 5, “CLK± Output
Phase Jitter,” on page 4.
Added Typical Phase Noise performance data in
Table 5, “CLK± Output Phase Jitter,” on page 4.
Updated 3. "Ordering Information" on page 8.
Removed ordering option E at VDD = 2.5 V in table for
the 2nd Option Code.
Typical APRs replaced with minimum APR values.
New 135 ppm/V KV option included.
Si550
Preliminary Rev. 0.3
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet SI550.PDF ] | |
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