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PDF CS61884 Data sheet ( Hoja de datos )

Número de pieza CS61884
Descripción Octal T1/E1/J1 Line Interface Unit
Fabricantes Cirrus Logic　
Logotipo Cirrus Logic Logotipo



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CS61884
Octal T1/E1/J1 Line Interface Unit
Features
Description
Industry Standard Footprint
Octal E1/T1/J1 Short-haul Line Interface Unit
Low Power
No External Component Changes for
100 Ω/120 Ω/75 Ω Operation
Pulse Shapes can be customized by the user
Internal AMI, B8ZS, or HDB3 Encoding/Decoding
LOS Detection per T1.231, ITU G.775, ETSI 300-233
G.772 Non-Intrusive Monitoring
G.703 BITS Clock Recovery
Crystal-less Jitter Attenuation
Serial/Parallel Microprocessor Control Interfaces
Transmitter Short Circuit Current Limiter (<50mA)
TX Drivers with Fast High-Z and Power Down
JTAG Boundary Scan compliant to IEEE 1149.1
144-Pin LQFP or 160-Pin BGA Package
ORDERING INFORMATION
CS61884-IQ
CS61884-IB
144-pin LQFP
160-pin FBGA
The CS61884 is a full-featured Octal E1/T1/J1 short-
haul LIU that supports both 1.544 Mbps or 2.048 Mbps
data transmission. Each channel provides crystal-less
jitter attenuation that complies with the most stringent
standards. Each channel also provides internal
AMI/B8ZS/HDB3 encoding/decoding. To support en-
hanced system diagnostics, channel zero can be
configured for G.772 non-intrusive monitoring of any of
the other 7 channels’ receive or transmit paths.
The CS61884 makes use of ultra low power matched im-
pedance transmitters and receivers to reduce power
beyond that achieved by traditional driver designs. By
achieving a more precise line match, this technique also
provides superior return loss characteristics. Additional-
ly, the internal line matching circuitry reduces the
external component count. All transmitters have controls
for independent power down and High-Z.
Each receiver provides reliable data recovery with over
12 dB of cable attenuation. The receiver also incorpo-
rates LOS detection compliant to the most recent
specifications.
Note: Click on any text in blue to go to cross-references.
LOS
RCLK
RPOS
RNEG
TCLK
TPOS
TNEG
JTAG
Serial
Port
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JTAG Interface
Host Interface
RTIP
RRING
TTIP
TRING
Host
Serial/Parallel
Port
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
©Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAY ‘02
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CS61884 pdf
CS61884
LIST OF FIGURES
Figure 1. CS61884 144-Pin Outs ....................................................................................................... 7
Figure 2. CS61884 160-Ball FBGA Pin Outs .................................................................................... 8
Figure 3. G.703 BITS Clock Mode in NRZ Mode .......................................................................... 23
Figure 4. G.703 BITS Clock Mode in RZ Mode ............................................................................. 23
Figure 5. G.703 BITS Clock Mode in Remote Loopback ............................................................... 23
Figure 6. Pulse Mask at T1/J1 Interface .......................................................................................... 24
Figure 7. Pulse Mask at E1 Interface .............................................................................................. 24
Figure 8. Analog Loopback Block Diagram .................................................................................... 30
Figure 9. Analog Loopback with TAOS Block Diagram ................................................................ 30
Figure 10. Digital Loopback Block Diagram .................................................................................. 31
Figure 11. Digital Loopback with TAOS ........................................................................................ 31
Figure 12. Remote Loopback Block Diagram ................................................................................. 31
Figure 13. Serial Read/Write Format (SPOL = 0) ........................................................................... 33
Figure 14. Arbitrary Waveform UI .................................................................................................. 43
Figure 15. Test Access Port Architecture ........................................................................................ 45
Figure 16. TAP Controller State Diagram ....................................................................................... 46
Figure 17. Internal RX/TX Impedance Matching ............................................................................ 51
Figure 18. Internal TX, External RX Impedance Matching ............................................................ 52
Figure 19. Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 ........................... 58
Figure 20. Jitter Tolerance Characteristic vs. G.823 & AT&T 62411 ............................................ 58
Figure 21. Recovered Clock and Data Switching Characteristics ................................................... 60
Figure 22. Transmit Clock and Data Switching Characteristics ...................................................... 60
Figure 23. Signal Rise and Fall Characteristics ............................................................................... 60
Figure 24. Serial Port Read Timing Diagram .................................................................................. 61
Figure 25. Serial Port Write Timing Diagram ................................................................................. 61
Figure 26. Parallel Port Timing - Write; Intel Multiplexed Address / Data Bus Mode ................... 63
Figure 27. Parallel Mode Port Timing - Read; Intel Multiplexed Address / Data Bus Mode ........ 63
Figure 28. Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus .................. 64
Figure 29. Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus ................... 64
Figure 30. Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode ....... 66
Figure 31. Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode ........ 66
Figure 32. Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode 67
Figure 33. Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode . 67
Figure 34. JTAG Switching Characteristics .................................................................................... 68
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CS61884 arduino
CS61884
SYMBOL
MUX/BITSEN0
INT
RDY/ACK/SDO
LQFP FBGA TYPE
DESCRIPTION
43 K2
Multiplexed Interface/Bits Clock Select
Host Mode -This pin configures the microprocessor inter-
face for multiplexed or non-multiplexed operation.
Hardware mode - This pin is used to enable channel 0 as
a G.703 BITS Clock recovery channel (Refer to BUILDING
INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE
I (See Section 8 on page 23). Channel 1 through 7 are not
affected by this pin during hardware mode. During host
mode the G.703 BITS Clock recovery function is enabled by
the Bits Clock Enable Register (1Eh) (See Section 14.31
on page 41).
Table 2. Mux/Bits Clock Selection
Pin State
HIGH
LOW
Parallel Host Mode
multiplexed
non multiplexed
Hardware Mode
BITS Clock ON
BITS Clock OFF
NOTE: The MUX pin only controls the BITS Clock function in
Hardware Mode
Interrupt Output
This active low output signals the host processor when one
of the CS61884’s internal status register bits has changed
82 K13 O state. When the status register is read, the interrupt is
cleared. The various status changes that would force INT
active are maskable via internal interrupt enable registers.
NOTE: This pin is an open drain output and requires a 10 kΩ
pull-up resistor.
Data Transfer Acknowledge/Ready/Serial Data Output
Intel Parallel Host Mode - During a read or write register
access, RDY is asserted “Low” to acknowledge that the de-
vice has been accessed. An asserted “High” acknowledges
that data has been written or read. Upon completion of the
bus cycle, this pin High-Z.
Motorola Parallel Host Mode - During a data bus read
operation this pin “ACK” is asserted “High” to indicate that
data on the bus is valid. An asserted “Low” on this pin dur-
ing a write operation acknowledges that a data transfer to
83
K14
O
the addressed register has been accepted. Upon comple-
tion of the bus cycle, this pin High-Z.
NOTE: Wait state generation via RDY/ACK is disabled in
RZ mode (No Clock Recovery).
Serial Host Mode - When the microprocessor interface is
configured for serial bus operation, “SDO” is used as a seri-
al data output. This pin is forced into a high impedance
state during a serial write access. The CLKE pin controls
whether SDO is valid on the rising or falling edge of SCLK.
Upon completion of the bus cycle, this pin High-Z.
Hardware Mode - This pin is not used and should be left
open.
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