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PDF CS61880 Data sheet ( Hoja de datos )
| Número de pieza | CS61880 | |
| Descripción | OCTAL E1 LINE INTERFACE UNIT | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS61880
Octal E1 Line Interface Unit
Features
Description
Octal E1 Short-haul Line Interface Unit
Low Power
No External Component Changes for 120 Ω / 75 Ω
Operation
Pulse Shapes can be customized by the user
Internal AMI, or HDB3 Encoding/Decoding
LOS Detection per ITU G.775 or ETSI 300- 233
G.772 Non-Intrusive Monitoring
G.703 BITS Clock Recovery
Crystal-less Jitter Attenuation
Serial/Parallel Microprocessor Control Interfaces
Transmitter Short Circuit Current Limiter (<50 mA)
TX Drivers with Fast High-Z and Power Down
JTAG Boundary Scan compliant to IEEE 1149.1
144-Pin LQFP or 160-Pin FBGA Package
ORDERING INFORMATION
CS61880-IQ
CS61880-IB
144-pin LQFP
160-pin FBGA
The CS61880 is a full-featured Octal E1 short-haul LIU
that supports 2.048 Mbps data transmission for both E1
75 Ω and E1 120 Ω applications. Each channel provides
crystal-less jitter attenuation that complies with the most
stringent standards. Each channel also provides internal
AMI/HDB3 encoding/decoding. To support enhanced
system diagnostics, channel zero can be configured for
G.772 non-intrusive monitoring of any of the other 7
channels’ receive or transmit paths.
The CS61880 makes use of ultra low power matched im-
pedance transmitters and receivers to reduce power
beyond that achieved by traditional driver designs. By
achieving a more precise line match, this technique also
provides superior return loss characteristics. Additional-
ly, the internal line matching circuitry reduces the
external component count. All transmitters have controls
for independent power down and High-Z.
Each receiver provides reliable data recovery with over
12 dB of cable attenuation. The receiver also incorpo-
rates LOS detection compliant to the most recent
specifications.
LOS
RCLK
RPOS
RNEG
TCLK
TPOS
TNEG
JTAG
Serial
Port
0
1
7
Jitter
Attenuator
LOS
Clock
Recovery
Receiver
Data
Recovery
Transmit
Control
Pulse
Shaper
Driver
JTAG Interface
Host Interface
RTIP
RRING
TTIP
TRING
Host
Serial/Parallel
Port
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
JUL ‘03
DS450PP3
1
1 page  
CS61880
LIST OF FIGURES
Figure 1. CS61880 144-Pin LQFP Package Pin Outs .................................................................... 7
Figure 2. CS61880 160-Ball FBGA Package Pin Outs ................................................................... 8
Figure 3. G.703 BITS Clock Mode in NRZ Mode .......................................................................... 23
Figure 4. G.703 BITS Clock Mode in RZ Mode............................................................................. 23
Figure 5. G.703 BITS Clock Mode in Remote Loopback .............................................................. 23
Figure 6. Pulse Mask at E1 Interface ............................................................................................ 24
Figure 7. Analog Loopback Block Diagram................................................................................... 30
Figure 8. Analog Loopback with TAOS Block Diagram................................................................. 30
Figure 9. Digital Loopback Block Diagram .................................................................................... 31
Figure 10. Digital Loopback with TAOS ........................................................................................ 31
Figure 11. Remote Loopback Block Diagram ............................................................................... 31
Figure 12. Serial Read/Write Format (SPOL = 0) ......................................................................... 33
Figure 13. Arbitrary Waveform UI ................................................................................................. 42
Figure 14. Test Access Port Architecture...................................................................................... 44
Figure 15. TAP Controller State Diagram ..................................................................................... 45
Figure 16. Internal RX/TX Impedance Matching ........................................................................... 50
Figure 17. Internal TX, External RX Impedance Matching............................................................ 51
Figure 18. Jitter Transfer Characteristic vs. G.736 & TBR 12/13 .................................................. 56
Figure 19. Jitter Tolerance Characteristic vs. G.823..................................................................... 57
Figure 20. Recovered Clock and Data Switching Characteristics................................................. 59
Figure 21. Transmit Clock and Data Switching Characteristics .................................................... 59
Figure 22. Signal Rise and Fall Characteristics ............................................................................ 59
Figure 23. Serial Port Read Timing Diagram ................................................................................ 60
Figure 24. Serial Port Write Timing Diagram ................................................................................ 60
Figure 25. Parallel Port Timing - Write; Intel® Multiplexed Address / Data Bus Mode ................. 62
Figure 26. Parallel Port Timing - Read; Intel Multiplexed Address / Data Bus Mode.................... 62
Figure 27. Parallel Port Timing - Write; Motorola® Multiplexed Address / Data Bus Mode .......... 63
Figure 28. Parallel Port Timing - Read; Motorola Multiplexed Address / Data Bus Mode............. 63
Figure 29. Parallel Port Timing - Write; Intel Non-Multiplexed Address / Data Bus Mode ............ 65
Figure 30. Parallel Port Timing - Read; Intel Non-Multiplexed Address / Data Bus Mode ............ 65
Figure 31. Parallel Port Timing - Write; Motorola Non-Multiplexed Address / Data Bus Mode ..... 66
Figure 32. Parallel Port Timing - Read; Motorola Non-Multiplexed Address / Data Bus Mode ..... 66
Figure 33. JTAG Switching Characteristics................................................................................... 67
Figure 34. 160-Ball FBGA Package Drawing................................................................................ 69
Figure 35. 144-Pin LQFP Package Drawing ................................................................................. 70
DS450PP3
5
5 Page 
CS61880
SYMBOL
MUX/BITSEN0
INT
RDY/ACK/SDO
LQFP FBGA TYPE
DESCRIPTION
43 K2
Multiplexed Interface/Bits Clock Select
Host Mode -This pin configures the microprocessor inter-
face for multiplexed or non-multiplexed operation.
Hardware mode - This pin is used to enable channel 0 as
a G.703 BITS Clock recovery channel (Refer to BUILDING
INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE
I (See Section 8 on page 23). Channel 1 through 7 are not
affected by this pin during hardware mode. During host
mode the G.703 BITS Clock recovery function is enabled by
the Bits Clock Enable Register (1Eh) (See Section 14.31
on page 40).
Table 2. Mux/Bits Clock Selection
Pin State Parallel Host Mode
HIGH
multiplexed
LOW
non multiplexed
Hardware Mode
BITS Clock ON
BITS Clock OFF
NOTE: The MUX pin only controls the BITS Clock function in
Hardware Mode
Interrupt Output
This active low output signals the host processor when one
of the CS61880’s internal status register bits has changed
82 K13 O state. When the status register is read, the interrupt is
cleared. The various status changes that would force INT
active are maskable via internal interrupt enable registers.
NOTE: This pin is an open drain output and requires a 10 kΩ
pull-up resistor.
Ready/Data Transfer Acknowledge/Serial Data Output
Intel Parallel Host Mode - During a read or write register
access, RDY is asserted “Low” to acknowledge that the de-
vice has been accessed. An asserted “High” acknowledges
that data has been written or read. Upon completion of the
bus cycle, this pin High-Z.
Motorola Parallel Host Mode - During a data bus read
operation this pin, “ACK”, is asserted “High” to indicate that
data on the bus is valid. An asserted “Low” on this pin dur-
ing a write operation acknowledges that a data transfer to
83
K14
O
the addressed register has been accepted. Upon comple-
tion of the bus cycle, this pin High-Z.
NOTE: Wait state generation via RDY/ACK is disabled in
RZ mode (No Clock Recovery).
Serial Host Mode - When the microprocessor interface is
configured for serial bus operation, “SDO” is used as a seri-
al data output. This pin is forced into a high impedance
state during a serial write access. The CLKE pin controls
whether SDO is valid on the rising or falling edge of SCLK.
Upon completion of the bus cycle, this pin High-Z.
Hardware Mode - This pin is not used and should be left
open.
DS450PP3
11
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| PDF Descargar | [ Datasheet CS61880.PDF ] | |
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